38.1 Rev. A - 04/2021

• Initial document release

• ATtiny202/402 Data Sheet
• ATtiny204/404 Data Sheet
• ATtiny406 Data Sheet

• ATtiny202/204/402/404/406 Data Sheet (this document)

The following items are referring to changes between the latest revisions of the obsolete documents and this document:

• Updated the document to Microchip editing standard
• Updated terminology used throughout data sheet:
  • Master is replaced by host
  • Slave is replaced by client
• Removed related links
• Removed the Acronyms and Abbreviations section
• Removed the content of the Instruction Set Summary section. This section now refers to the external Instruction Set Manual instead.
• Removed device-specific information from peripheral sections
• Restructured sections related to system dependencies within the peripheral sections

• Restructured/changed device-specific information to comply with the devices documented in this document
  • Features
  • Pinout
  • I/O Multiplexing and Considerations
  • Ordering Information
  • Package Drawings
• Updated Block diagram
• Updated Pinout diagrams:
  • 8-Pin SOIC
  • 14-Pin SOIC
  • 20-Pin SOIC
  • 20-Pin VQFN
• Memories
  • Added Memory Map figure ⁽³⁾
  • Moved Memory Section Access from CPU and UPDI on Locked Device section to after General Purpose I/O Register n section
  • Update Fuse Description section with factory-programmed default values
• Peripherals and Architecture
  • Updated Peripheral Address Match table
    • Correct typo in the Base Address for AC0 from 0x680 to 0x670
  • Updated Interrupt Vector Mapping table
    • Base Address column renamed to Program Address (word)
    • Peripheral Source column cleaned up
    • Definition column renamed to Description and cleaned up
• Package Drawings
  • Updated Drawing Numbers table
  • Removed tables as the information is available on the Microchip website:
    • Device Package and Maximum Weight
    • Package Characteristics
    • Package Reference
  • Updated Thermal Considerations section and moved inside the Package Drawings section

• Updated Features section
• Removed duplicate information after the AVR CPU architecture
• Emphasized that the Arithmetic Logic Unit (ALU) is doing its operations against working registers in the register file
• Added Stack Pointer Instructions table
• Restructured and improved documentation in the following sections:
  • Register File
  • X-, Y-, and Z-Registers
  • Accessing 16-bit Registers
• Added Accessing 24-Bit Registers section
• Added On-Chip Debug Capabilities section
• Updated bit names in the Status Register (SREG):
  • From Bit Copy Storage to Transfer Bit
  • From Sign Bit to Sign Flag

• Updated CLKCTRL Block Diagram figure^(1,2)
• Updated Signal Description section^(1,2)
• Updated Main Clock and Prescaler figure⁽¹⁾
• Updated External Clock Sources section⁽¹⁾
• Updated CLKSEL bit field in MCLKCTRLA register⁽¹⁾
• Added CLKOUT bit in MCLKCTRLA^(1,2)

• Updated Sleep Mode Activity Overview tables

• Updated Block Diagram figure
• Figures added:
  • MCU Start-up, RESET Tied to V_DD
  • Brown-out Detector Reset
  • External Reset Characteristics
  • Watchdog Reset
  • Software Reset
• Added Domains Affected By Reset section

• Added Minimum Interrupt Response Time table
• General improvement of the documentation and its structure

• Corrected in Features section the number of synchronous and asynchronous channels^(1,2,3)
• Register names updated
  • From ASYNCCH to ASYNCCHn
  • From SYNCCH to SYNCCHn
  • From ASYNCUSER to ASYNCUSERn
  • From SYNCUSER to SYNCUSERn
• Bit field descriptions updated
  • ASYNCCHn.ASYNCCH
  • SYNCCHn.SYNCCH

• Removed non-available TCA05 and TCA04 bits in the CTRLC register⁽³⁾
• General improvement of the documentation

• Updated Block Diagram figure
• Added Asynchronous Sensing Pin Properties section
• Added Event Generators in PORTx table
• General improvement of the documentation and its structure

• Block diagram updated
• Offset in the Available Interrupt Vectors and Sources table removed
• Name column added to bit field description tables:
  • CTRLA.ACTIVE
  • CTRLA.SLEEP
  • INTCTRL.VLMCFG

• Updated values in the CTRLA.PERIOD bit field description

• Updated Block Diagram figure
• Updated Timer/Counter Clock Logic figure
• Updated Signal Description table
• Update Single-Slope Pulse-Width Modulation figure
• Updated Timer/Counter Block Diagram Split Mode figure
• Added Event Generators in TCA table
• Added Event Users in TCA table
• Removed offset in the Available Interrupt Vectors and Sources in Normal Mode and Available Interrupt Vectors and Sources in Split mode tables
• Combined tables for the CTRLB.WGMODE bit field into one
• Added bit fields:
  • CTRLECLR.CMDEN
  • CTRLESET.CMDEN
• General improvement of the documentation and its structure

• Updated Block Diagram figure
• Timer/Counter Clock Logic figure added
• Figures updated:
  • Periodic Interrupt Mode
  • Time-Out Check Mode
  • Input Capture on Event
  • Input Capture Frequency Measurement
  • Input Capture Pulse-Width Measurement
  • Input Capture Frequency and Pulse-Width Measurement
  • Single-Shot Mode
  • 8-Bit PWM Mode
• Added Event Generators in TCB table
• Added Event Users and Available Event Actions in TCB table
• Removed offset in the Available Interrupt Vectors and Sources table
• Name column added to bit field description tables:
  • CTRLA.CLKSEL
  • CTRLB.CNTMODE

• Updated Block Diagram figure
• Event Generators in RTC table added
• Removed offset in the Available Interrupt Vectors and Sources table
• Added name column to the bit field description table for CLKSEL.CLKSEL
• General improvement of the documentation and its structure

• Added information about TXD buffer in:
  • Block Diagram figure
  • Overview section
  • Data Transmission section
• Event Generators in USART table added
• Event Users in USART table added
• Offset in the Available Interrupt Vectors and Sources table removed
• General improvement of the documentation and its structure
• Updated terminology:
  • Master is replaced by host
  • Slave is replaced by client

• Updated Block Diagram figure
• Added Event Generators in SPI table
• Removed offset in the Available Interrupt Vectors and Sources table
• Interrupt Flags register separate for Normal and Buffer mode
• General improvement of the documentation and its structure
• Updated terminology:
  • Master is replaced by host
  • Slave is replaced by client

• Offset in the Available Interrupt Vectors and Sources table removed
• Name column added to bit field description tables:
  • CTRLA.FMPEN
  • MCTRLB.ACKACT
  • MCTRLB.MCMD
• General improvement of the documentation and its structure
• Updated terminology:
  • Master is replaced by host
  • Slave is replaced by client

• Updated Block Diagram figure⁽¹⁾
• Offset in the Available Interrupt Vectors and Sources table removed

• Updated Block Diagram figure
• Replaced Lookup Table Logic section with Truth Table Logic section
• Updated Clock Source Settings figure
• Updated bit field description of TRUTHn.TRUTHn

• Updated figures:
  • UPDI Clock Domains
  • UPDI Instruction Set Overview
  • LDS Instruction Operation
  • STS Instruction Operation
  • LD Instruction Operation
  • ST Instruction Operation
  • LCDS Instruction Operation
  • STCS Instruction Operation
  • REPEAT Instruction Operation
  • Inter Delay Example with LD and RPT
• Added sections:
  • BREAK in One-Wire mode
  • SYNCH and SYNCH in One-Wire mode
• Extended and improved the documentation related to enabling the UPDI peripheral
• Extended and improved the documentation related to disabling the UPDI peripheral
• Renamed the UPDI Enable with 12V Override of RESET pin section to UPDI Enable with High-Voltage Override of RESET pin
• Added the REPEAT Used With LD Instruction Operation figure
• Added Event Generators in UPDI table
• Removed implementation-specific details that are considered as not useful for the end users

• Added Maximum Frequency vs. V_DD for [-40, 125]°C, Extended Temperature Range figure
• Added maximum numbers in the Power Consumption section
• In the Peripherals Power Consumption table:
  • Rounded typical numbers
  • Added OSCULP32K
• Updated TWI - Timing Requirements figure
• Updated numbers for t_OF in the TWI - Timing Characteristics table
• Added typical values for t_HD;STA, t_SU;STA, t_SU;STO and t_BUF
• Added SDA Hold Time table
• Added TEMPSENSE section
• Updated tables in the AC section
• Added UPDI Max. Bit Rates vs. VDD table
• Replaced Chip Erase with Chip Erase with UPDI in the Programming Times table

• Updated Power Consumption plots
• Added Temperature Sensor Error vs. Temperature ±3σ figure
• Added TWI SDA Hold Time vs. Temperature figure