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tinyAVR® 0-series ATtiny202/204/402/404/406
Introduction
Features
1 Silicon Errata and Data Sheet Clarification Document
2 tinyAVR® 0-series Overview
2.1 Configuration Summary
3 Block Diagram
4 Pinout
4.1 8-Pin SOIC
4.2 14-Pin SOIC
4.3 20-Pin SOIC
4.4 20-Pin VQFN
5 I/O Multiplexing and Considerations
5.1 Multiplexed Signals
6 Memories
6.1 Overview
6.2 Memory Map
6.3 In-System Reprogrammable Flash Program Memory
6.4 SRAM Data Memory
6.5 EEPROM Data Memory
6.6 User Row
6.7 Signature Bytes
6.8 I/O Memory
6.9 Memory Section Access from CPU and UPDI on Locked Device
6.10 Configuration and User Fuses (FUSE)
7 Peripherals and Architecture
7.1 Peripheral Address Map
7.2 Interrupt Vector Mapping
7.3 System Configuration (SYSCFG)
8 AVR® CPU
8.1 Features
8.2 Overview
8.3 Architecture
8.4 Arithmetic Logic Unit (ALU)
8.5 Functional Description
8.6 Register Summary
8.7 Register Description
9 NVMCTRL - Nonvolatile Memory Controller
9.1 Features
9.2 Overview
9.3 Functional Description
9.4 Register Summary
9.5 Register Description
10 CLKCTRL - Clock Controller
10.1 Features
10.2 Overview
10.3 Functional Description
10.4 Register Summary
10.5 Register Description
11 SLPCTRL - Sleep Controller
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Register Summary
11.5 Register Description
12 RSTCTRL - Reset Controller
12.1 Features
12.2 Overview
12.3 Functional Description
12.4 Register Summary
12.5 Register Description
13 CPUINT - CPU Interrupt Controller
13.1 Features
13.2 Overview
13.3 Functional Description
13.4 Register Summary
13.5 Register Description
14 EVSYS - Event System
14.1 Features
14.2 Overview
14.3 Functional Description
14.4 Register Summary
14.5 Register Description
15 PORTMUX - Port Multiplexer
15.1 Overview
15.2 Register Summary
15.3 Register Description
16 PORT - I/O Pin Configuration
16.1 Features
16.2 Overview
16.3 Functional Description
16.4 Register Summary - PORTx
16.5 Register Description - PORTx
16.6 Register Summary - VPORTx
16.7 Register Description - VPORTx
17 BOD - Brown-out Detector
17.1 Features
17.2 Overview
17.3 Functional Description
17.4 Register Summary
17.5 Register Description
18 VREF - Voltage Reference
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary
18.5 Register Description
19 WDT - Watchdog Timer
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Register Summary - WDT
19.5 Register Description
20 TCA - 16-bit Timer/Counter Type A
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary - Normal Mode
20.5 Register Description - Normal Mode
20.6 Register Summary - Split Mode
20.7 Register Description - Split Mode
21 TCB - 16-Bit Timer/Counter Type B
21.1 Features
21.2 Overview
21.3 Functional Description
21.4 Register Summary
21.5 Register Description
22 RTC - Real-Time Counter
22.1 Features
22.2 Overview
22.3 Clocks
22.4 RTC Functional Description
22.5 PIT Functional Description
22.6 Events
22.7 Interrupts
22.8 Sleep Mode Operation
22.9 Synchronization
22.10 Debug Operation
22.11 Register Summary
22.12 Register Description
23 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
23.1 Features
23.2 Overview
23.3 Functional Description
23.4 Register Summary
23.5 Register Description
24 SPI - Serial Peripheral Interface
24.1 Features
24.2 Overview
24.3 Functional Description
24.4 Register Summary
24.5 Register Description
25 TWI - Two-Wire Interface
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary
25.5 Register Description
26 CRCSCAN - Cyclic Redundancy Check Memory Scan
26.1 Features
26.2 Overview
26.3 Functional Description
26.4 Register Summary - CRCSCAN
26.5 Register Description
27 CCL - Configurable Custom Logic
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary
27.5 Register Description
28 AC - Analog Comparator
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary
28.5 Register Description
29 ADC - Analog-to-Digital Converter
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary - ADCn
29.5 Register Description
30 UPDI - Unified Program and Debug Interface
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary
30.5 Register Description
31 Instruction Set Summary
32 Conventions
32.1 Numerical Notation
32.2 Memory Size and Type
32.3 Frequency and Time
32.4 Registers and Bits
32.5 ADC Parameter Definitions
33 Electrical Characteristics
33.1 Disclaimer
33.2 Absolute Maximum Ratings
33.3 General Operating Ratings
33.4 Power Consumption
33.5 Wake-Up Time
33.6 Peripherals Power Consumption
33.7 BOD and POR Characteristics
33.8 External Reset Characteristics
33.9 Oscillators and Clocks
33.10 I/O Pin Characteristics
33.11 USART
33.12 SPI
33.13 TWI
33.14 VREF
33.15 ADC
33.16 TEMPSENSE
33.17 AC
33.18 UPDI Timing
33.19 Programming Time
34 Typical Characteristics
34.1 Power Consumption
34.2 GPIO
34.3 VREF Characteristics
34.4 BOD Characteristics
34.5 ADC Characteristics
34.6 TEMPSENSE Characteristics
34.7 AC Characteristics
34.8 OSC20M Characteristics
34.9 OSCULP32K Characteristics
34.10 TWI SDA Hold Timing
35 Ordering Information
35.1 Product Information
35.2 Product Identification System
36 Package Drawings
36.1 Online Package Drawings
36.2 8-Pin SOIC
36.3 14-Pin SOIC
36.4 20-Pin SOIC
36.5 20-Pin VQFN
36.6 Thermal Considerations
37 Errata
37.1 Errata - ATtiny202/204/402/404/406
38 Data Sheet Revision History
38.1 Rev. A - 04/2021
38.2 Appendix - Obsolete Revision History
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