20.7.2 Control B - Split Mode

Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -

Bit 76543210 
  HCMP2ENHCMP1ENHCMP0EN LCMP2ENLCMP1ENLCMP0EN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 6 – HCMP2EN High byte Compare 2 Enable

See HCMP0EN.

Bit 5 – HCMP1EN High byte Compare 1 Enable

See HCMP0EN.

Bit 4 – HCMP0EN High byte Compare 0 Enable

Setting the HCMPnEN bit in the FRQ or PWM Waveform Generation mode of operation will override the port output register for the corresponding WO[n+3] pin.

Bit 2 – LCMP2EN Low byte Compare 2 Enable

See LCMP0EN.

Bit 1 – LCMP1EN Low byte Compare 1 Enable

See LCMP0EN.

Bit 0 – LCMP0EN Low byte Compare 0 Enable

Setting the LCMPnEN bit in the FRQ or PWM Waveform Generation mode of operation will override the port output register for the corresponding WOn pin.