Jump to main content
20.14.5 TMRxCLK Timer Clock Source
Selection Register Name: TMRxCLK Offset: 0xFD2,0xFCC,0xFC6,0xF33
Bit 7 6 5 4 3 2 1 0 CS[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0
Bits 3:0 – CS[3:0] Timer Clock Source Selection
bits
CS Clock
Source Timer1 Timer3 Timer5 Timer7 1111-1101Reserved Reserved Reserved Reserved 1100TMR7 overflow TMR7 overflow TMR7 overflow Reserved 1011TMR5 overflow TMR5 overflow Reserved TMR5 overflow 1010TMR3 overflow Reserved TMR3 overflow TMR3 overflow 1001Reserved TMR1 overflow TMR1 overflow TMR1 overflow 1000TMR0 overflow TMR0 overflow TMR0 overflow TMR0 overflow 0111CLKREF CLKREF CLKREF CLKREF 0110SOSC SOSC SOSC SOSC 0101MFINTOSC (500 kHz) MFINTOSC (500 kHz) MFINTOSC (500 kHz) MFINTOSC (500 kHz) 0100LFINTOSC LFINTOSC LFINTOSC LFINTOSC 0011HFINTOSC HFINTOSC HFINTOSC HFINTOSC 0010Fosc Fosc Fosc Fosc 0001Fosc/4 Fosc/4 Fosc/4 Fosc/4 0000T1CKIPPS T3CKIPPS T5CKIPPS T7CKIPPS
Reset States: POR/BOR = 0000 All Other Resets = uuuu
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
