5 Interacting with Pins, Peripherals and the CPU

5.1 Interacting with Pins

The CLB does not have direct access to input or output pins on the MCU. All interaction between the CLB and pins is done using the PPS module.

5.1.1 Input from Pins to the CLB

Using the value of a pin in the CLB.

Four PPS input channels can be used in the CLB and are made available in the CLB Synthesizer in the Input Ports selector.

Note: Configure the PPS module to select the required input pin on the MCU.

Input signals from PPS pass through the Input Synthronizers upon entering the CLB. For more information, see Input Synchronizers.

5.1.2 Output to Pins from the CLB

Driving a pin from the CLB.

The CLB can use eight PPS output channels. They are made available in the CLB Synthesizer in the Output Ports selector.

Note: Configure the PPS module to select the required output pin on the MCU.

5.1.3 Controlling the TRIS Register

Enable and disable the pin output driver to drive a tri-state bus.

Each PPS_OUT signal in the CLB Synthesizer has a corresponding PPS_OE signal, which can be used to enable or disable the pin output driver using the TRIS register.

Configure the OESEL field of the CLBPPSCON register to select which BLE output controls the TRIS signal. MCC will do this automatically, while the web version users can find this mapping in the clb1_output_mappings.h file inside the ZIP. This ZIP can be downloaded after synthesis.

Note: It is not possible to use the high-impedence 'Z' state in Verilog for purposes of tristating signals.

5.2 Interacting with Peripherals

Interaction with other peripherals is done by using the input ports from other peripherals and output ports to other peripherals in a logic design. Consult the device datasheet for information on how these signals are used by the corresponding peripheral.

5.2.1 Input Synchronizers

Making use of synchronizers on input signals.

The CLB peripheral includes 16 input sources, which connect the CLB to external signals and the 32 CLBSWIN signals for interacting with the CPU. The 16 input sources include modifiers that can condition the incoming signal before entering the BLE matrix.

Input synchronizer options are selected on the right-side properties panel below the input port source selection box.

The following table shows the available input synchronizer options:

Table 5-1. Input Synchronizer Options
Option	Description
Synchronized input	The input signal will be synchronized to the CLB clock, which is the default and safest option when unsure
Direct input	Synchronization is bypassed, and the input signal is connected directly to the BLE input. As this can cause metastability in sequential logic designs, use it carefully.
Positive edge detector	A rising edge on the input signal will generate a pulse synchronized to the CLB clock
Negative edge detector	A falling edge on the input signal will generate a pulse synchronized to the CLB clock

Note:

The CLBSWIN signals cannot pass through the input synchronizers
The input synchronizer is selected in hardware with three configuration bits, but not all eight possible permutations are made available in the CLB Synthesizer

5.2.2 CLB Outputs to other Peripherals

How to route signals from the CLB to other peripheral modules.

The CLB BLE outputs can be connected to various other peripherals, which is a two-stage process:

Step 1: Configure an Output From the CLB

In the CLB Synthesizer GUI, configure an output port by selecting the peripheral signal to route to in the port properties panel.

Synthesize the logic design.

Step 2: Configure the Peripheral to Accept the Signal From the CLB

The peripheral to which the CLB connects must be configured to receive the CLB input signal, which is Peripheral-dependent. Consult the data sheet for more information.

The peripheral input selector usually specifies a range of BLEs that can be used as inputs from the CLB. It is not up to the user to specify this - the place and route algorithm must hit one of these BLEs to satisfy the criteria for using the peripheral. The actual BLE, which was realized during synthesis, receives the synthesis output.

MCC Users

After synthesis, check the notifications window for information on configuring other peripherals.

Web/Bare-Metal Users

Users of the web version need to download the ZIP output from the synthesis process and examine (or use directly) the contents of clb1_output_mappings.h file, which provides values for use in the peripheral configuration register.

5.3 Interacting with the CPU

Interaction between the CPU (running code) and the CLB using the CLBSWIN register.

5.3.1 Using CLBSWIN

How to use CLBSWIN from the MCU.

The CLB Software Input register (CLBSWIN) enables the MCU to communicate directly with the logic design in the CLB. So for example, this can be used to load a 'value' into the CLB at run time.

To make use of the CLBSWIN register within a logic design, simply use the individual CLBSWINn bits as input ports.

If a logic design needs to trigger an action when a new value is written to CLBSWIN, then the CLBSWIN_SFR_WR_HOLD input signal can be used. This signal is asserted when the CPU writes a new value to CLBSWIN and that value have been latched into the CLB.

Note:

The CLBSWIN register cannot be used via the input synchronizers
The CLBSWIN_SFR_WR_HOLD signal is asserted only when the lower eight bits of CLBSWIN are written (CLBSWINL), so the byte must be written after writing the upper bytes in CLBSWIN