3 The Synthesis Process, Status and Outputs

3.1 Status of the Synthesis Process

Understanding the synthesis status indicator.

A synthesis process converts a logic design into bitstream form, which can be loaded into the CLB. Clicking the Synthesize button will trigger this.

The status indicator and the resource view indicate the outcome of the synthesis process.

Successful Synthesis

A green indicator will show when the synthesis succeeds - and the resource view is updated.

The resource view indicates how much of the CLB’s resources are used, and hovering the mouse over it gives additional information.

Tip: The synthesis process stops once a solution is found, and no further optimization is done. The number of resources used may be higher than expected.

Failed Synthesis

A red indicator will show when synthesis has failed.

The nature of the failure can be determined by:

Checking the Design checker or Notifications panels for warnings about unconnected pins
Checking the Synthesis panel for output from the backend synthesis process
Downloading the ZIP and checking the backend log output, which must also be included when consulting Microchip support channels

Tip: Selecting the entry in the Design Checker panel highlights the component or port that may be causing the problem.

3.2 Synthesis Outputs

Additional outputs other than the bitstream.

The primary output of the Synthesis process is the bitstream. However, there are additional outputs in the ZIP file which may be useful.

Two diagrams are produced during synthesis and displayed in the output panel on the left sidebar.

pre-routing.svg

This diagram shows a presentation of your logic design after YoSYS has processed it but before mapping it into CLB-specific resources.

In this example, the three inputs are presented to the 3-input LUT3 via nodes mapping 'P' to 'O' and the output of the LUT connected to PPS_OUT0 via a node mapping 'I' to 'P'. These nodes are virtual connections unmapped onto hardware resources.

routed.svg

This diagram shows a representation of your logic as it will be implemented on the actual CLB hardware using its available resources.

This example implements the same logic design as the previous one. In this diagram, it is clear that:

CLBIN1PPS is connected directly to the A input of the LUT
PWM1_OUT is connected via BLE9 to the B input of the LUT (as shown by the expression 'O = A')
CLBIN0PPS is connected via BLE18 to the C input of the LUT (as shown by the expression 'O = A')
The logic expression is performed by BLE6 and its logic expression is O = 'C + 'A + B
The LUT output is connected to PPS_OUT0 via BLE2

Flip-flops are labeled with DFF in the diagrams.

By counting the number of BLEs that the logic signals pass through between synchronization points (flip-flops) it is possible to estimate a safe operating frequency for the logic design in conjunction with timing information in the device data sheet.

3.3 Resource Usage Debugging

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When using the CLB Synthesizer, the place and route algorithm in the backend synthesis process is done by resource allocation. Determining the reason for failure can be complicated since some resources are locked to individual BLE outputs or a range of BLE outputs. Therefore, a small logic design cannot be synthesized if these resources are in conflict (technically, this is a failure to complete place-and-route). In cases where synthesis fails, these actions can be taken to try to alleviate the conflict and reach a solution:

Try to use alternative outputs (e.g., change IRQ0 to IRQ1)
Try to remove some logic functionality
Check that there are no unused modules included in the documents
Check that there are no logic functions with pre-determined outputs (e.g., a constant zero as an input to an AND gate)

Include the ZIP file returned from the failing synthesis process when contacting Microchip support.