Silicon Errata Issues

The following errata issues apply to the PIC32CX-BZ6 family of devices.

Note:
  • Cells with an ‘X’ indicate the issue is present in this revision of the silicon.
  • Cells with a dash (‘—’) indicate the issue does not exist for this revision of the silicon.
  • Blank cells indicate the issue is corrected or does not exist in this revision of the silicon.
Note: Traditional Inter-Integrated Circuit (I2C) and Serial Peripheral Interface (SPI) documentation uses the terminology “Master” and “Slave”. The equivalent Microchip terminology used in this document is “Host” and “Client” respectively.

Analog-to-Digital Converter (ADC)

Glitches in ADC Conversion Result

When the ADC control clock is asynchronous with the system clock, the conversion result may have glitches if a new conversion result updates while the CPU reads ADCDATAx.

Work Around

The user must accurately read ADCBUFx before the next conversion begins. If the ADC is operated in the Asynchronous mode, ensure that each converted value is read immediately after the ready bit is set. Achieve this either by implementing a tight polling loop or by using low-latency interrupts.

Affected Silicon Revisions

A0
X

Configurable Custom Logic (CCL)

PAC Error when Writing to CCL.CTRLA.SWRST Bit

Writing to the Software Reset bit in the Control A register (CTRLA.SWRST) of the CCL triggers a Peripheral Access Controller (PAC) protection error.

Work Around

Clear the CCL PAC error each time a CCL software Reset is executed.

Affected Silicon Revisions

A0
X

The LUT Output is Corrupted after Enabling the CCL when using Sequential Logic

When the LUT is disabled (LUTCTRL0.ENABLE = 0) to clear the flip-flop or latch output and then enabled again, the sequential logic remains under Reset.

Work Around

Write to CTRL.ENABLE again after the LUT is enabled (after LUTCTRL0.ENABLE = 1).

Affected Silicon Revisions

A0
X

Controller Area Network (CAN)

Debug Message Handling State Machine Not Resetting

In case CCCR.INIT bit is set by writing to the CCCR register or when the M_CAN enters Bus Off state, the debug message handling state machine stays in its current state, as signaled by RXF1S.DMS, instead of being reset to the Idle state. If RXF1S.DMS = 3, the output m_can_dma_req remains active. Setting CCCR.CCE does not change RXF1S.DMS.

This behavior is limited to when the debug on CAN Support feature is active. Regular operation is not affected. In regular operation, the debug message handling state machine always remains in the Idle state.

Work Around

If the debug message handling state machine stops while RXF1S.DMS = 1 or RXF1S.DMS = 2, the user can reset it to the Idle state either by performing hardware reset or by receiving debug messages after resetting CCCR.INIT to zero.

If the debug message handling state machine stops while RXF1S.DMS = 3 with m_can_dma_req active, the user can reset it to the Idle state either by performing a hardware reset or by activating the input m_can_dma_ack.

Affected Silicon Revisions

A0
X

Message Order Inversion when Transmitting with Same Message ID

Several Tx buffers are configured with the same Message ID. Transmission of these Tx buffers is requested sequentially with a delay between the individual Tx requests. Depending on the delay between the individual Tx requests, it can happen that when multiple Tx buffers are configured with the same Message ID, the Tx buffers are not transmitted in the order of the Tx buffer number (lowest number first).

Work Around

First, write the group of Tx messages with the same Message ID to the Message RAM, and then request the transmission of all these messages concurrently by a single write access to TXBAR.

Use the Tx FIFO instead of the dedicated Tx buffers for the transmission of several messages with the same Message ID in a specific order. For more details, refer to the Section 3.5.3 Tx FIFO of the M_CAN Controller Area Network User’s Manual (Revision 3.3.1).

Affected Silicon Revisions

A0
X

Interrupt Access to Reserved Area

When the reserved register space is accessed, the IR.ARA bit is not asserted and it returns zero.

Work Around

None.

Affected Silicon Revisions

A0
X

Direct Memory Access Controller (DMAC)

Fetch Error on Linked Descriptors

When at least one channel using linked descriptors is already active, enabling a channel with no linked descriptor or having one of the already active channels using linked descriptors fetch the enabled second descriptor (index 1) of the channel may cause a channel Fetch Error (FERR). These errors may occur if a channel is enabled during the link request of another channel and if the channel number of the enabled channel is lower than that of the already active channel.

Work Around

When enabling a channel while other channels using linked descriptors are already active, the channel number of the new channel to enable must be greater than the other channel numbers.

Affected Silicon Revisions

A0
X

Corrupted DMA Writeback Descriptor

Writeback descriptors can be corrupted on an active channel where there is an ongoing transfer while another channel is being disabled or suspended.

Work Around

None.

Affected Silicon Revisions

A0
X

Event System (EVSYS)

Spurious Overrun Interrupts

In the Synchronous mode, spurious overrun interrupts can happen when the generic clock for a channel is always CHANNEL.ONDEMAND = 0.

Work Around

Set generic clock On Demand feature by setting CHANNEL.ONDEMAND = 1.

Affected Silicon Revisions

A0
X

Software Event

The BUSYCH flag never resets upon software events in synchronous or resynchronized path modes with event detection on falling edges.

If a software event occurs when the EVSYS is set to synchronous or resynchronized path modes (CHANNELn.PATH = 0x0/0x1) with event detection set to falling edges (CHANNELn.EDGSEL = 0x2), the CHSTATUS.BUSYCHn flag is set but never returns to 0. As a result, it is impossible to determine whether the event user for this channel is ready to accept new events.

Work Around

Generate software events for this user through a dedicated channel configured with event detection set to rising edges (CHANNELn.EDGSEL = 0x1).

Affected Silicon Revisions

A0
X

Spurious Overrun

The Overrun Interrupt flag may be incorrectly set upon software events in the Synchronous/Resynchronized Path modes with event detection on both rising and falling edges.

If a software event occurs when the EVSYS is set to Synchronous/Resynchronized Path modes (CHANNELn.PATH = 0x0/0x1) with event detection set to both rising and falling edges (CHANNELn.EDGSEL = 0x3), spurious overrun interrupts may occur (INTFLAG.OVRn).

Work Around

Generate software events for the event user through a dedicated channel configured with event detection set on rising edges (CHANNELn.EDGSEL = 0x1).

Affected Silicon Revisions

A0
X

External Interrupt Controller (EIC)

Asynchronous Edge Detection

When asynchronous edge detection is enabled and the system is in Standby Sleep mode, only the first edge is detected. Edges following the first edge of the waveform are ignored until the system wakes up.

Work Around

Use asynchronous edge detection with the debouncer enabled. The recommendation is to set DPRESCALER.PRESCALER and DPRESCALER.TICKON to achieve the lowest frequency possible. To reduce power consumption, set the EIC GCLK frequency as low as possible or select the 32KHz_LPCLK clock (with EIC CTRLA.CKSEL set).

Affected Silicon Revisions

A0
X

Spurious NMI Interrupts

If the NMI is configured in the Synchronous Edge Detection mode (NMICTRL.NMISENSE = 1, 2, or 3; NMICTRL.NMIASYNCH = 0), spurious NMI interrupts may occur after a software Reset (CTRLA.SWRST = 1).

Work Around

  1. Configure one dummy EIC external interrupt x (EXTINTx) in the Edge Detection mode.
  2. Enable the EIC (CTRLA.ENABLE = 1).
  3. Wait for synchronization to complete (SYNCBUSY.ENABLE = 0).
  4. Configure the NMI in the Edge Detection mode.

Affected Silicon Revisions

A0
X

General-Purpose Input/Output (GPIO)

GPIO Port Value Unstable in Debug and Freeze Mode

The issue occurs when a signal changes on a GPIO pad at the same time that the MPLAB® In-Circuit Debugger (ICD) freezes the GPIO peripheral. In this case, reading the port register results in unstable values for the pads that changed.

Work Around

None.

Affected Silicon Revisions

A0
X

Peripheral Access Controller (PAC)

PAC Protection Error in FREQM

FREQM reads on the Control B register (FREQM.CTRLB) to generate a PAC protection error.

Work Around

None.

Affected Silicon Revisions

A0
X

RAM Error Correction Code (RAMECC)

4 Bytes Not Retained at Address 0x20000018

When SRAM is configured for memory retention, 4 bytes of memory cannot be retained.

Work Around

For ease-of-use, retention memory for deep sleep applications or similar applications should start at SRAM offset of 32 bytes.

Affected Silicon Revisions

A0
X

Real-Time Counter and Calendar (RTCC)

Tamper Input Filter Majority Debouncing Not Working

Majority debouncing, as part of the RTCC tamper detection, does not work when enabled by setting the Debouncer Majority Enable bit, CTRLB.DEBMAJ.

Work Around

None.

Affected Silicon Revisions

A0
X

False Tamper Detection

Enabling the RTCC tamper detection feature can cause the RTCC to report a false tamper detection.

Work Around

Use any one of the following workarounds:

  • Configure TAMPER detection to ONLY falling edge.
  • If the user software has to use TAMPER detection as the rising edge, it must ignore the first tamper interrupt generated after enabling the RTCC tamper detection.

Affected Silicon Revisions

A0
X

Periodic Event Generation when CTRLA.PRESCALER is OFF

When CTRLA.PRESCALER is set to OFF and either CTRLB.RTCOUT is set or one of the TAMPCTRL.DEBNCn bits is set, the RTCC prescaler behaves like CTRLA.PRESCALER = DIV1. The periodic events and periodic interrupts are generated.

Work Around

Clear the EVTCTRL.PEREOn bits to avoid unwanted event generation, and clear the INTENCLR.PERn bits to avoid unwanted interrupt generation.

Affected Silicon Revisions

A0
X

INFLAG.TAMPER Not Resetting

When DMA is enabled (CTRLB.DMAEN = 1), the INTFLAG.TAMPER bit does not reset after reading the TIMESTAMP register.

Work Around

Clear the INTFLAG.TAMPER bit by writing a 1 to this bit when the timestamp value is read by the DMA.

Affected Silicon Revisions

A0
X

SYNCBUSY Register in Deep Sleep Mode

Entering the Deep Sleep mode without waiting for the synchronization completion of SYNCBUSY.ENABLE and SYNCBUSY.COUNTSYNC may freeze these bits status.

Work Around

The user must always configure and enable the RTCC before enabling the Deep Sleep mode.

Affected Silicon Revisions

A0
X

Periodic Daily Event Generated One Second Earlier

For prescaler values above DIV1, the system must assert the periodic delay event at the end of the prescaler period to generate it on the last second of the day. Since the prescaler overflow does not qualify the periodic delay event, the system generates the event at the beginning of the prescaler period, causing it to occur one second earlier than specified.

Work Around

None.

Affected Silicon Revisions

A0
X

ACTL Detection not Gated by rtc_enable

When the RTC is configured in ACTL mode with an external tamper pin and the RTC CTRLA.ENABLE bit is not set, a tamper can be detected and a timestamp captured. The TAMPID register and the INTFLAG.TAMPER bit may, but are not always, be set.

Work Around

When the RTC is configured for tamper detection in ACTL mode with an external pin, after setting the CTRLA.ENABLE control bit, the user must wait for 10 RTC clock periods.

Then the user clears the TAMPID register, clear the INTFLAG.TAMPER bit, and performs a dummy read of the TIMESTAMP register to remove the Lock condittion on the TIMESTAMP register. After these operations, the RTC tamper is configured and running.

Affected Silicon Revisions

A0
X

Write Corruption

An 8-bit or 16-bit write access to a 32-bit register, or an 8-bit write access to a 16-bit register, can fail for the following registers:
  • COUNT register in COUNT32 mode
  • COUNT register in COUNT16 mode
  • CLOCK register in CLOCK mode

Work Around

Write to the registers as follows:
  • Use a 32-bit write access for the COUNT register in COUNT32 mode and the CLOCK register in CLOCK mode.
  • Use a 16-bit write access for the COUNT register in COUNT16 mode.

Affected Silicon Revisions

A0
X

Tamper Detection Timestamp

If an external Reset occurs during tamper detection, the TIMESTAMP register is not updated when the next tamper detection is triggered.

Work Around

Enable the RTC tamper interrupt and copy the timestamp from the RTC CLOCK register to one of the following destinations:
  • SRAM
  • GPx register in the RTC
  • BKUPx register in the RTC

Affected Silicon Revisions

A0
X

General Purpose Register

General Purpose registers n (GPn) are reset on tamper detection even if GPTRST = 0.

Work Around

None.

Affected Silicon Revisions

A0
X

COUNTSYNC

When COUNTSYNC is enabled, the first COUNT value is not correctly synchronized and is therefore incorrect.

Work Around

After enabling COUNTSYNC, read the COUNT register repeatedly until its value changes from the first value read. After this, all subsequent reads from the COUNT register are valid.

Affected Silicon Revisions

A0
X

Serial Communication Interface (SERCOM)

SERCOM-I2C: Repeated Start

When the Quick command is enabled (CTRLB.QCEN = 1), the software can issue a repeated Start by writing to either CTRLB.CMD or ADDR.ADDR bit fields. If, under these conditions, the SCL Stretch mode is CTRLA.SCLSM = 1, a bus error is generated.

Work Around

Use the Quick Command mode (CTRLB.QCEN = 1) only if the SCL Stretch mode (CTRLA.SCLSM) is set to 0.

Affected Silicon Revisions

A0
X

SERCOM-I2C: Client in DATA32B Mode Stalled Bus

When SERCOM is configured as an I2C client in the 32-bit Data mode (DATA32B = 1) and the I2C host reads from the I2C client (client transmitter) and outputs its NACK (indicating no more data is needed), the I2C client still receives a DRDY interrupt.

If the CPU does not write new data to the I2C client DATA register, the I2C client pulls the SDA line, resulting in a permanent bus stall.

Work Around

Use any one of the following workarounds:

  • Write dummy data to the Data register when the host sends a NACK signal.
  • Use command #2 (SERCOMx->I2CS.CTRLB.CMD = 2) when the host sends a NACK signal.
Important: Since STATUS.RXNACK always indicates the last received ACK, the I2C client software must consider I2CS.STATUS.RXNACK only on the second DRDY interrupt after receiving the AMATCH interrupt to determine when the I2C host has sent a NACK.

Affected Silicon Revisions

A0
X

SERCOM-I2C: Client Auto ACK is Not Usable

The I2C client’s AACKEN feature is not usable when doing a repeated start.

Work Around

Do not use the AACKEN feature; instead, implement an AMATCH handler.

Affected Silicon Revisions

A0
X

SERCOM-I2C: Client Error Interrupt INTFLAG.ERROR Repeated Start

When an unexpected STOP occurs on the I2C bus, the STATUS.BUSERR and INTFLAG.ERROR bits are set but may not wake the system from Standby Sleep mode. An unexpected START does not produce this issue.

Work Around

None.

Affected Silicon Revisions

A0
X

SERCOM-I2C: I2C in Client Mode

In I2C mode, the LENERR, SEXTOUT, LOWTOUT, COLL, and BUSERR bits are not cleared when INTFLAG.AMATCH is cleared.

Work Around

Manually clear the following status bits by writing 1 to each bit when they are set:
  • LENERR
  • SEXTOUT
  • LOWTOUT
  • COLL
  • BUSERR

Affected Silicon Revisions

A0
X

SERCOM-I2C: Client Mode with DMA

In the I2C Client Transmitter mode, upon reception of a NACK, if there is still data to be sent in the DMA buffer, the DMA pushes data to the DATA register. Because a NACK was received, the transfer on the I2C bus does not occur, causing the loss of this data.

Work Around

Configure the DMA transfer size to match the number of data bytes to be received by the I2C host. The DMA cannot be used if the number of data bytes to be received by the host is unknown.

Affected Silicon Revisions

A0
X

SERCOM-USART: Data Transmission in Debug Mode

In the USART Operating mode, if DBGCTRL.DBGSTOP = 1, the data transmission is not halted after entering the Debug mode.

Work Around

None.

Affected Silicon Revisions

A0
X

SERCOM-USART: Two Stop Bits Mode Not Supported in LIN Operation

Two stop bits mode (CTRLB.SBMODE = 1) is not supported in the SERCOM USART LIN Host mode (CTRLA.FORM = 2) when the break, sync, and identifier fields are automatically transmitted when DATA is written with the identifier (CTRLB.LINCMD = 2). Only One Stop Bit mode is supported.

Work Around

None.

Affected Silicon Revisions

A0
X

SERCOM-USART: Collision Detection

In the USART Operating mode with Collision Detection Enabled (CTRLB.COLDEN = 1), the SERCOM does not abort the current transfer as expected if a collision is detected and the SERCOM APB (PBx_CLK) clock is lower than the SERCOM generic clock.

Work Around

The SERCOM APB (PBx_CLK) clock must always be higher than the SERCOM generic clock to support collision detection.

Affected Silicon Revisions

A0
X

SERCOM-USART: Error Interrupts

The SERCOM USART does not wake from Standby Sleep mode for ERROR interrupts, such as Framing Error (FERR) and Parity Error (PERR).

Work Around

Configure the SERCOM-USART to wake up on RX complete and check for any PERR or FERR Interrupt flags upon wake-up.

Affected Silicon Revisions

A0
X

SERCOM-USART: Flow Control in 32-Bit Extension Mode

When the USART is used in 32-bit mode with hardware handshaking, Clear To Send (CTS)/Request To Send (RTS), the TXC flag may be set before transmission has completed. TXC may be incorrectly set regardless of whether Data Length Enable (LENGTH.LENEN) is set to 0 or 1.

Work Around

Use 8-bit mode when using Hardware Flow Control feature.

Affected Silicon Revisions

A0
X

SERCOM-USART: SERCOM USART in TX Mode Only

When the SERCOM USART is configured with CTRLA.RUNSTDBY = 0 and the receiver is disabled (CTRLB.RXEN = 0), the clock request to the SERCOM generic clock generator feeding the SERCOM remains asserted during Standby Sleep mode, leading to unexpected overconsumption.

Work Around

Configure CTRLA.RXPO and CTRLA.TXPO to use the same SERCOM pad for RX and TX, or add an external pull-up on the RX pin.

Affected Silicon Revisions

A0
X

SERCOM-SPI: 32-Bit Extension Mode Additional Bytes

When the 32-bit Extension mode is enabled and the data to be sent is not in multiples of 4 bytes, which means the length counter must be enabled, additional bytes are sent over the line.

Work Around

Use any one of the following workarounds:
  • Write the Inter-Character Spacing bits (CTRLC.ICSPACE) to a non-zero-value.
  • Do not use the length counter in firmware by keeping the data to be sent in multiples of 4 bytes.

Affected Silicon Revisions

A0
X

SERCOM-SPI: Client Data Preload

Preloading new SPI data (CTRLB.PLOADEN = 1) before entering Standby Sleep mode may lead to increased power consumption.

Work Around

None.

Affected Silicon Revisions

A0
X

SERCOM-SPI: Data Preload

In SPI Client mode with Client Data Preload Enabled (CTRLB.PLOADEN = 1), the client transmitter may discard some data if the host cannot keep the Client Select (SS) pin low until the end of the transmission.

Work Around

In SPI Client mode, the Client Select pin (SS) must be kept low by the host until the end of the transmission in case of using the Client Data Preload feature (CTRLB.PLOADEN = 1).

Affected Silicon Revisions

A0
X

SERCOM-SPI: Hardware Client Select Control

When hardware Client Select Control is enabled (CTRLB.MSSEN = 1), the Client Select (SS) pin goes high after each byte transfer, even if new data is ready to be sent.

Work Around

Set CTRLB.MSSEN to 0 and handle the Client Select (SS) pin in software.

Affected Silicon Revisions

A0
X

SERCOM-I2C Client: I2C DRDY Raised when no Data is to be Fed

The RXNACK status bit is invalid during the first I2CS_DRDY interrupt handler.

Work Around

Use a software flag to track when to ignore RXNACK (equivalent to having it true), and reset this flag in the I2CS_AMATCH interruption handler (this workaround inapplicable with AACKEN = 1).

Affected Silicon Revisions

A0
X

SERCOM-I2C Client: SCL/SDA Transition Time

The minimum transition time for SCL/SDA is not met in Fast-mode Plus (1 MHz).

Work Around

If desired, external series resistors can slow the falling transition. Ensure that REXT × CLOAD is greater than 13 ns, and do not exceed 1 kΩ for REXT.
Table . SERCOM Output Low Current (IOLmin) vs. VDDIO Voltage Range
Product/InterfaceVoltage RangeIOLmin
All SERCOM (except SERCOM2)2.97 < VDDIO < 3.6316.3 mA
1.9 < VDDIO < 2.979.3 mA
SERCOM22.97 < VDDIO < 3.6320mA
1.9 < VDDIO < 2.9713mA

Affected Silicon Revisions

A0
X

Supply Voltage and Power Mode

GPIO Change Notification Interrupt not Firing After Sleep

The issue occurs when CNEN0x = 110 or 101. The device does not wake up on a Pin state change.
  • When CNEN0x = 110, interrupt-on-change for a negative edge transition is enabled for PORTx[n].
  • When CNEN0x = 101, interrupt-on-change for a positive edge transition is enabled for PORTx[n].

Work Around

When CNEN0x = 110, interrupt-on-change for a negative edge transition is enabled for PORTx[n]. Keep the PORT value high before entering the Sleep mode so that the negative edge can be detected.

When CNEN0x = 101, interrupt-on-change for a positive edge transition is enabled for PORTx[n]. Keep the PORT value low before entering the Sleep mode so that the positive edge can be detected.

Affected Silicon Revisions

A0
X

Timer/Counter (TC)

SYNCBUSY Flag on PERBUF/CCBUFx Register

When clearing the STATUS.PERBUFV/STATUS.CCBUFVx flag, the SYNCBUSY flag is released before restoring the PERBUF/CCBUFx register to its appropriate value.

Work Around

Clear the STATUS.PERBUFV/STATUS.CCBUFVx flag twice successively to ensure that the system restores the PERBUF/CCBUFx register value before updating it.

Affected Silicon Revisions

A0
X

Corrupted Re-trigger Event Waveform Output

If a Re-trigger event (EVCTRL.EVACTn = 1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next waveform output [n] is corrupted.

Work Around

Use two channels to store their two successive (n and n+1) CC register values and combine their related waveform outputs to make signal redundancy.

Affected Silicon Revisions

A0
X

Timer/Counter for Control Applications (TCC)

Dithering Mode with External Re-trigger Events

Using the TCC in the Dithering mode with external re-trigger events can lead to an unexpected stretch of right-aligned pulses or shrink of left-aligned pulses.

Work Around

Do not use re-trigger events or actions when the TCC module is configured in the Dithering mode.

Affected Silicon Revisions

A0
X

LUPD Feature in Down-Counting Mode

When the TCC is used in the Down-counting mode, the transfer of the PERBUF register value to the PER register is delayed by one counter cycle; therefore, do not use the LUPD feature with the PER register.

Work Around

In the Down-counting mode, write period value directly to the PER register instead of writing to the PERBUF register. Alternatively, the Up-counting mode in the TCC can be used if the LUPD feature is required.

Affected Silicon Revisions

A0
X

Incompatible with EVSYS in SYNC/RESYNC Mode

The TCC peripheral is not compatible with an EVSYS channel in the SYNC or RESYNC mode.

Work Around

Use the TCC with an EVSYS channel in the ASYNC mode.

Affected Silicon Revisions

A0
X

2RAMP Mode with Hi-resolution Reference Multiple Restarts

In the two Ramp modes (RAMP2, RAMP2A, RAMP2C, and RAMP2CS), a re-trigger is not supported in the Dithering mode.

Work Around

None.

Affected Silicon Revisions

A0
X

Corrupted Re-trigger Event Waveform Output

If a Re-trigger event (EVCTRL.EVACTn = 1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted.

Work Around

Use two channels to store their two successive (n and n+1) CC register values and combine their related waveform outputs to make signal redundancy.

Affected Silicon Revisions

A0
X

RAMP2 Feature in Down-Counting Mode

The Timer/Counter Counting-down mode (CTRLBCLR.DIR = CTRLBSET.DIR = 1) is not supported in RAMP2 operations (RAMP2, RAMP2A, RAMP2C, and RAMP2CS).

Work Around

Use the Timer/Counter Up-counting mode (CTRLBCLR.DIR = CTRLBSET.DIR = 0).

Affected Silicon Revisions

A0
X

Watchdog Timer (WDT)

Run Mode Watchdog Counter is Not Cleared Before Standby Sleep Instruction

When the interval between clearing the WDT (in other words, clearing the Run mode watchdog counter) and the sleep instruction is less than one WDT clock cycle, the Run mode watchdog counter is not cleared. When using Low-Power RC Oscillator (LPRC) as a clock source, the interval is one LPRC clock. Since the watchdog timer is in the LPRC domain, which is much slower than the CPU clock, the sleep instruction is executed even before clearing the Run mode watchdog counter. Hence, the Run mode watchdog counter remains frozen at its last count instead of clearing to 0.

While in the Standby Sleep mode, the Sleep mode watchdog counter increments. At the end of the Watchdog Timer Postscaler (WDTPS), it generates a Non-Maskable Interrupt (NMI), which causes the CPU to wake up.

After wake-up, the user expects that because the WDT is cleared just before going to sleep, an entire WDT period is available before the WDT needs to be cleared again. However, because the Run mode counter is not cleared before going into sleep, the WDT Reset occurs earlier than expected.

Work Around

Use any one of the following workarounds:
  • Add a delay of more than one WDT Clock (LPRC clock) between clearing of the WDT and execution of sleep instruction.
  • Execute the WDT clear instruction as soon as the CPU wakes up.

Affected Silicon Revisions

A0
X