1 Silicon Errata Summary
| Module | Feature | Issue Summary | Affected Revisions | |
|---|---|---|---|---|
| PIC32CX2051BZ62132, PIC32WM-BZ6204 | ||||
| A0 | ||||
| Analog-to-Digital Converter (ADC) | Glitches in ADC Conversion Result | When the ADC control clock is asynchronous with the system clock, the conversion result may have glitches if the CPU reads ADCBUFx while a new conversion result is being updated. | X | |
| Configurable Custom Logic (CCL) | PAC Error when Writing to CCL.CTRLA.SWRST Bit | Writing to the Software Reset bit in the Control A register (CTRLA.SWRST) of the CCL triggers a PAC protection error. | X | |
| Configurable Custom Logic (CCL) | The LUT Output is Corrupted after Enabling the CCL when using Sequential Logic | When the LUT is disabled
(LUTCTRL0.ENABLE = 0 or LUTCTRL2.ENABLE =
0) to clear the flip-flop or latch output and then
enabled again, the sequential logic remains under Reset. | X | |
| Controller Area Network (CAN) | Debug Message Handling State Machine Not Resetting |
In case bit CCCR.INIT is set by writing to the CCCR register or when the M_CAN enters the Bus Off state, the debug message handling state machine stays in its current state, as signaled by RXF1S.DMS, instead of being reset to the Idle state. If RXF1S.DMS = 3, the output m_can_dma_req remains active. Setting CCCR.CCE does not change RXF1S.DMS. This behavior is limited to when the debug on CAN Support feature is active. Regular operation is not affected. In regular operation, the debug message handling state machine always remains in the Idle state. | X | |
| Controller Area Network (CAN) | Message Order Inversion when Transmitting with Same Message ID |
Several Tx buffers are configured with the same Message ID. Transmission of these Tx buffers is requested sequentially with a delay between the individual Tx requests. Depending on the delay between the individual Tx requests, it can happen that when multiple Tx buffers are configured with the same Message ID, the Tx buffers are not transmitted in the order of the Tx buffer number (lowest number first). | X | |
| Controller Area Network (CAN) | Interrupt Access to Reserved Area | When the reserved register space is accessed, the IR.ARA bit is not asserted and it returns zero. | X | |
| Direct Memory Access Controller (DMAC) | Fetch Error on Linked Descriptors | When at least one channel using linked descriptors is already active, enabling a channel with no linked descriptor or having one of the already active channels using linked descriptors fetch the enabled second descriptor (index 1) of the channel may cause a channel Fetch Error (FERR). These errors may occur if a channel is enabled during the link request of another channel and if the channel number of the enabled channel is lower than that of the already active channel. | X | |
| Direct Memory Access Controller (DMAC) | Corrupted DMA Writeback Descriptor | Writeback descriptors can be corrupted on an active channel where there is an ongoing transfer while another channel is being disabled or suspended. | X | |
| Event System (EVSYS) | Spurious Overrun Interrupts | In the Synchronous mode, spurious
overrun interrupts can happen when the generic clock for a channel is
always CHANNEL.ONDEMAND = 0. | X | |
| Event System (EVSYS) | Software Event |
The BUSYCH flag never resets upon software events in synchronous or resynchronized path modes with event detection on falling edges. If a software event occurs when the EVSYS is set to synchronous or
resynchronized path modes (CHANNELn.PATH = 0x0/0x1) with event
detection set to falling edges (CHANNELn.EDGSEL = 0x2), the
CHSTATUS.BUSYCHn flag is set but never returns to
| X | |
| Event System (EVSYS) | Spurious Overrun | The Overrun Interrupt flag may be
incorrectly set upon software events in the Synchronous/Resynchronized
Path modes with event detection on both rising and falling edges. If a software event occurs when the EVSYS is set to Synchronous/Resynchronized Path modes (CHANNELn.PATH = 0x0/0x1) with event detection set to both rising and falling edges (CHANNELn.EDGSEL = 0x3), spurious overrun interrupts may occur (INTFLAG.OVRn). | X | |
| External Interrupt Controller (EIC) | Asynchronous Edge Detection | When asynchronous edge detection is enabled and the system is in Standby Sleep mode, only the first edge is detected. Edges following the first edge of the waveform are ignored until the system wakes up. | X | |
| External Interrupt Controller (EIC) | Spurious NMI Interrupts | If the NMI is configured in the
Synchronous Edge Detection mode (NMICTRL.NMISENSE = 1, 2, or 3;
NMICTRL.NMIASYNCH = 0), spurious NMI interrupts may
occur after a software Reset (CTRLA.SWRST = 1). | X | |
| General-Purpose Input/Output (GPIO) | GPIO Port Value Unstable in Debug and Freeze Mode | The issue occurs when a signal changes on a GPIO pad at the same time that the MPLAB In-Circuit Debugger (ICD) freezes the GPIO peripheral. In this case, reading the port register results in unstable values for the pads that changed. | X | |
| Peripheral Access Controller (PAC) | PAC Protection Error in FREQM | FREQM reads on the Control B register (FREQM.CTRLB) to generate a PAC protection error. | X | |
| RAM Error Correction Code (RAMECC) | 4 Bytes Not Retained at Address 0x20000018 | When SRAM is configured for memory retention, 4 bytes of memory cannot be retained. | X | |
| Real-Time Counter and Calendar (RTCC) | Tamper Input Filter Majority Debouncing Not Working | Majority debouncing, as part of the RTCC tamper detection, does not work when enabled by setting the Debouncer Majority Enable bit, CTRLB.DEBMAJ. | X | |
| Real-Time Counter and Calendar (RTCC) | False Tamper Detection | Enabling the RTCC tamper detection feature can cause the RTCC to report a false tamper detection. | X | |
| Real-Time Counter and Calendar (RTCC) | Periodic Event Generation when CTRLA.PRESCALER is OFF | When CTRLA.PRESCALER is set to OFF and either CTRLB.RTCOUT is set or one of the TAMPCTRL.DEBNCn bits is set, the RTCC prescaler behaves like CTRLA.PRESCALER = DIV1. The periodic events and periodic interrupts are generated. | X | |
| Real-Time Counter and Calendar (RTCC) | INFLAG.TAMPER Not Resetting | When DMA is enabled (CTRLB.DMAEN =
1), the INTFLAG.TAMPER bit does not reset after
reading the TIMESTAMP register. | X | |
| Real-Time Counter and Calendar (RTCC) | SYNCBUSY Register in Deep Sleep Mode | Entering the Deep Sleep mode without waiting for the synchronization completion of SYNCBUSY.ENABLE and SYNCBUSY.COUNTSYNC may freeze these bits status. | X | |
| Real-Time Counter and Calendar (RTCC) | Periodic Daily Event Generated One Second Earlier | For prescaler values above DIV1, the system must assert the periodic delay event at the end of the prescaler period to generate it on the last second of the day. Since the prescaler overflow does not qualify the periodic delay event, the system generates the event at the beginning of the prescaler period, causing it to occur one second earlier than specified. | X | |
| Real-Time Counter and Calendar (RTCC) | ACTL Detection not Gated by rtc_enable | Clear the INTFLAG.TAMPER bit by writing a 1 to this bit after reading the timestamp value from the TIMESTAMP register. | X | |
| Real-Time Counter (RTCC) | Write Corruption | An 8-bit or 16-bit write access to a
32-bit register, or an 8-bit write access to a 16-bit register, can fail
for the following registers:
| X | |
| Real-Time Counter (RTCC) | Tamper Detection Timestamp | If an external Reset occurs during tamper detection, the TIMESTAMP register is not updated when the next tamper detection is triggered. | X | |
| Real-Time Counter (RTCC) | General Purpose Register | General Purpose registers n (GPn) are
reset on tamper detection even if GPTRST = 0. | X | |
| Real-Time Counter (RTCC) | COUNTSYNC | When COUNTSYNC is enabled, the first COUNT value is not correctly synchronized and is therefore incorrect. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Repeated Start | When the Quick command
is enabled (CTRLB.QCEN = 1), the software can issue a
repeated Start by writing to either CTRLB.CMD or ADDR.ADDR bit fields.
If, under these conditions, the SCL Stretch mode is CTRLA.SCLSM =
1, a bus error is generated. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Client in DATA32B Mode Stalled Bus |
When SERCOM is configured as an I2C client in the 32-bit
Data mode (DATA32B = If the CPU does not write new data to the I2C client DATA register, the I2C client pulls the SDA line, resulting in a permanent bus stall. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Client Auto ACK is Not Usable | The I2C client’s AACKEN feature is not usable when doing a repeated start. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Client Error Interrupt INTFLAG.ERROR Repeated Start | When an unexpected STOP occurs on the I2C bus, the STATUS.BUSERR and INTFLAG.ERROR bits are set but may not wake the system from Standby Sleep mode. An unexpected START does not produce this issue. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: I2C in Client Mode | In I2C mode, the LENERR, SEXTOUT, LOWTOUT, COLL, and BUSERR bits are not cleared when INTFLAG.AMATCH is cleared. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Client Mode with DMA | In the I2C Client Transmitter mode, upon reception of a NACK, if there is still data to be sent in the DMA buffer, the DMA pushes data to the DATA register. Because a NACK was received, the transfer on the I2C bus does not occur, causing the loss of this data. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Data Transmission in Debug Mode | In the USART Operating mode, if
DBGCTRL.DBGSTOP = 1, the data transmission is not
halted after entering the Debug mode. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Two Stop Bits Mode Not Supported in LIN Operation | Two stop bits mode (CTRLB.SBMODE = 1) is not supported in the SERCOM USART LIN Host mode (CTRLA.FORM = 2) when the break, sync, and identifier fields are automatically transmitted when DATA is written with the identifier (CTRLB.LINCMD = 2). Only One Stop Bit mode is supported. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Collision Detection | In the USART Operating mode with
Collision Detection Enabled (CTRLB.COLDEN = 1), the
SERCOM does not abort the current transfer as expected if a collision is
detected and the SERCOM APB (PBx_CLK) clock is lower than the SERCOM
generic clock. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Error Interrupts | The SERCOM USART does not wake from Standby Sleep mode for ERROR interrupts, such as Framing Error (FERR) and Parity Error (PERR). | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Flow Control in 32-Bit Extension Mode | When the USART is used in 32-bit mode
with hardware handshaking, Clear To Send (CTS)/Request To Send (RTS),
the TXC flag may be set before transmission has completed. TXC may be
incorrectly set regardless of whether Data Length Enable (LENGTH.LENEN)
is set to 0 or 1. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: SERCOM USART in TX Mode Only | When the SERCOM USART is configured with
CTRLA.RUNSTDBY = 0 and the receiver is disabled
(CTRLB.RXEN = 0), the clock request to the SERCOM
generic clock generator feeding the SERCOM remains asserted during
Standby Sleep mode, leading to unexpected overconsumption. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-SPI: 32-Bit Extension Mode Additional Bytes | When the 32-bit Extension mode is enabled and the data to be sent is not in multiples of 4 bytes, which means the length counter must be enabled, additional bytes are sent over the line. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Client Data Preload | Preloading new SPI data (CTRLB.PLOADEN =
1) before entering Standby Sleep mode may lead to
increased power consumption. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Data Preload | In SPI Client mode with Client Data
Preload Enabled (CTRLB.PLOADEN = 1), the client
transmitter may discard some data if the host cannot keep the Client
Select (SS) pin low until the end of the transmission. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Hardware Client Select Control | When hardware Client Select Control is
enabled (CTRLB.MSSEN = 1), the Client Select (SS) pin
goes high after each byte transfer, even if new data is ready to be
sent. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C Client: I2C DRDY Raised when no Data is to be Fed | The RXNACK status bit is invalid during the first I2CS_DRDY interrupt handler. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C Client: SCL/SDA Transition Time | The minimum transition time for SCL/SDA is not met in Fast-mode Plus (1 MHz). | X | |
| Supply Voltage and Power Mode | GPIO Change Notification Interrupt not Firing After Sleep | The issue occurs when CNEN0x =
110 or 101. The device does not wake up on
a Pin state change.
| X | |
| Timer/Counter (TC) | SYNCBUSY Flag on PERBUF/CCBUFx Register | When clearing the STATUS.PERBUFV/STATUS.CCBUFVx flag, the SYNCBUSY flag is released before restoring the PERBUF/CCBUFx register to its appropriate value. | X | |
| Timer/Counter (TC) | Corrupted Re-trigger Event Waveform Output | If a Re-trigger event (EVCTRL.EVACTn = 1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted. | X | |
| Timer/Counter for Control Applications (TCC) | Dithering Mode with External Re-trigger Events | Using the TCC in the Dithering mode with external re-trigger events can lead to an unexpected stretch of right-aligned pulses or shrink of left-aligned pulses. | X | |
| Timer/Counter for Control Applications (TCC) | LUPD Feature in Down-Counting Mode |
When the TCC is used in the Down-counting mode, the transfer of the PERBUF register value to the PER register is delayed by one counter cycle; therefore, do not use the LUPD feature with the PER register. | X | |
| Timer/Counter for Control Applications (TCC) | Incompatible with EVSYS in SYNC/RESYNC Mode | The TCC peripheral is not compatible with an EVSYS channel in the SYNC or RESYNC mode. | X | |
| Timer/Counter for Control Applications (TCC) | 2RAMP Mode with Hi-resolution Reference Multiple Restarts | In the 2RAMP mode with Hi-resolution, multiple restarts can be observed when a fault occurs. | X | |
| Timer/Counter for Control Applications (TCC) | Corrupted Re-trigger Event Waveform Output | If a Re-trigger event (EVCTRL.EVACTn =
1, RETRIGGER) occurs at the Channel Compare Match
[n] time, the next Waveform Output [n] is corrupted. | X | |
| Timer/Counter for Control Applications (TCC) | RAMP2 Feature in Down-Counting Mode |
The Timer/Counter Counting-down mode (CTRLBCLR.DIR = CTRLBSET.DIR =
| X | |
| Watchdog Timer (WDT) | Run Mode Watchdog Counter is Not Cleared Before Standby Sleep Instruction | When the interval between clearing the
WDT (in other words, clearing the Run mode watchdog counter) and the
sleep instruction is less than one WDT clock cycle, the Run mode
watchdog counter is not cleared. When using Low-Power RC Oscillator
(LPRC) as a clock source, the interval is one LPRC clock. Since the
watchdog timer is in the LPRC domain, which is much slower than the CPU
clock, the sleep instruction is executed even before clearing the Run
mode watchdog counter. Hence, the Run mode watchdog counter remains
frozen at its last count instead of clearing to 0.
While in the Standby Sleep mode, the Sleep mode watchdog counter increments. At the end of the Watchdog Timer Postscaler (WDTPS), it generates an Non-Maskable Interrupt (NMI), which causes the CPU to wake up. After wake-up, the user expects that because the WDT is cleared just before going to sleep, an entire WDT period available before the WDT needs to be cleared again. However, because the Run mode counter is not cleared before going into sleep, the WDT Reset occurs earlier than expected. | X | |
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