ATmega48PB/88PB/168PB

2.6.1 ADC Result Might Be Incorrect

ADC samples in the transition between 255-256 and 767-768 will, in very rare cases, give results where bit 8 is incorrectly read as 0, if the ADC clock is faster than 250 kHz.

Work around

Run the ADC clock at 250 kHz or slower, or collect multiple samples and discard the incorrect reading.

Table 2-1. Affected Silicon Revisions
ATmega48PB/88PB				ATmega168PB
Rev. A	Rev. B	Rev. K	Rev. M	Rev. A	Rev. B	Rev. C	Rev. N	Rev. O
X	X	X	X	X	X	X	X	X

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