1 Description
- MUL, multiplication of unsigned integers
- MULS, multiplication of signed integers
- MULSU, multiplication of a signed integer with an unsigned integer
- FMUL, multiplication of unsigned fractional numbers
- FMULS, multiplication of signed fractional numbers
- FMULSU, multiplication of a signed fractional number and with an unsigned fractional number
The MULSU and FMULSU instructions are included to improve the speed and code density for multiplication of 16-bit operands. The second section will show examples of how to efficiently use the multiplier for 16-bit arithmetic.
The component that makes a dedicated digital signal processor (DSP) specially suitable for signal processing is the Multiply-Accumulate (MAC) unit. This unit is functionally equivalent to a multiplier directly connected to an Arithmetic Logic Unit (ALU). The megaAVR microcontrollers are designed to give the AVR family the ability to effectively perform the same multiply-accumulate operation. This application note will therefore include examples of implementing the MAC operation.
The Multiply-Accumulate operation (sometimes referred to as multiply-add operation) has one critical drawback. When adding multiple values to one result variable, even when adding positive and negative values to some extent cancel each other, the risk of the result variable to overrun its limits becomes evident, i.e., if adding one to a signed byte variable that contains the value +127, the result will be -128 instead of +128. One solution often used to solve this problem is to introduce fractional numbers, i.e., numbers that are less than 1 and greater than or equal to -1. The final section presents some issues regarding the use of fractional numbers.
In addition to the new multiplication instruction, a few other additions and improvements are made to the megaAVR processor core. One improvement that is particularly useful is the instruction MOVW - Copy Register Word, which makes a copy of one register pair into another register pair.
The file “AVR201.asm” contains the application note source code of the 16-bit multiply routines.
A listing of all implementations with key performance specifications is given in the table below.
| 8-bit x 8-bit routines | Word [cycles) |
|---|---|
| Unsigned multiply 8 x 8 = 16 bits | 1 (2) |
| Signed multiply 8 x 8 = 16 bits | 1 (2) |
| Fractional signed/unsigned multiply 8 x 8 = 16 bits | 1 (2) |
| Fractional signed multiply-accumulate 8 x 8 = 16 bits | 3 (4) |
| 16-bit x 16-bit routines | |
| Signed/unsigned multiply 16 x 16 = 16 bits | 6 (9) |
| Unsigned multiply 16 x 16 = 32 bits | 13 (17) |
| Signed multiply 16 x 16 = 32 bits | 15 (19) |
| Signed multiply-accumulate 16 x 16 = 32 bits | 19 (23) |
| Fractional signed multiply 16 x 16 = 32 bits | 16 (20) |
| Fractional signed multiply-accumulate 16 x 16 = 32 bits | 21 (25) |
| Unsigned multiply 16 x 16 = 24 bits | 10 (14) |
| Signed multiply 16 x 16 = 24 bits | 10 (14) |
| Signed multiply-accumulate 16 x 16 = 24 bits | 12 (16) |