36.7.4 SPIxCLK

SPI Clock Selection Register

Name:	SPIxCLK
Offset:	0x08C,0x099


Bit	7	6	5	4	3	2	1	0
				CLKSEL[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CLKSEL[4:0] SPI Clock Source Selection

Table 36-5. SPI CLK Source Selections
CLK	Selection
`10111-11111`	Reserved
`10110`	CLC8_OUT
`10101`	CLC7_OUT
`10100`	CLC6_OUT
`10011`	CLC5_OUT
`10010`	CLC4_OUT
`10001`	CLC3_OUT
`10000`	CLC2_OUT
`01111`	CLC1_OUT
`01110`	SMT1_OUT
`01001-01111`	Reserved
`01110`	TU16B_OUT
`01101`	TU16A_OUT
`01000`	TMR6_Postscaler_OUT
`00111`	TMR4_Postscaler_OUT
`00110`	TMR2_Postscaler_OUT
`00101`	TMR0_OUT
`00100`	Clock Reference Output
`00011`	EXTOSC
`00010`	MFINTOSC (500 kHz)
`00001`	HFINTOSC
`00000`	F_OSC (System Clock)

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