36.7.8 SPIxSTATUS

SPI Status Register
Name: SPIxSTATUS
Offset: 0x087,0x094

Bit 76543210 
 TXWE TXBE RXRECLB RXBF 
Access R/C/HSRR/C/HSSR 
Reset 01000 

Bit 7 – TXWE Transmit Buffer Write Error

ValueDescription
1 SPIxTXB was written while TxFIFO was full
0 No error has occurred

Bit 5 – TXBE Transmit Buffer Empty

ValueDescription
1 Transmit buffer TxFIFO is empty
0 Transmit buffer is not empty

Bit 3 – RXRE Receive Buffer Read Error

ValueDescription
1 SPIxRXB was read while RxFIFO was empty
0 No error has occurred

Bit 2 – CLB Clear Buffer Control

ValueDescription
1 Reset the receive and transmit buffers, making both buffers empty
0 Take no action

Bit 0 – RXBF Receive Buffer Full

ValueDescription
1 Receive buffer is full
0 Receive buffer is not full