28.4.5.2 Reset Event

The Reset event for the counter/timer Reset is selected using the RESET bits in the TUxyHLT register. The Reset function dominates the operation of the counter.

The available options include:

  1. No hardware Reset: No hardware Reset of the counter/timer. The counter will continue to the full value and roll over to zero.
  2. ERS = 0 (level-triggered): The counter/timer resets at the presence of a logic zero of the ERS signal and/or when the TUxyTMR counter register is equal to the TUxyPR period register. When the EPOL bit is set, the polarity is inverted and the counter/timer resets at the presence of a logic one of the ERS signal. This prevents any start event from advancing the counter and RUN bit is held at zero. See Figure 28-9 for an example of a level-triggered ERS Reset.(2)
  3. At a start event: The counter/timer resets at the first clock of the counter/timer start and/or when the TUxyTMR counter register is equal to the TUxyPR period register. The number of cycles needed to reach PR match is extended by one. If the Start condition is ERS = 1 (or ERS = 0, based on EPOL selection), the Reset will only apply to the leading ERS edge. See Figure 28-11 for an example of Reset at a Start event.(2)
  4. At period match: The counter/timer resets when TUxyTMR counter register is equal to the TUxyPR period register.
Important:
  1. If the counter is already zero, a Reset event will not trigger ZIF interrupt.
  2. When prescaler > 0, then any ERS or Start-based Reset event that occurs during a PR match period will reset the timer counter and prescaler counter immediately, and the pulse output will not occur. If the Reset event collides with the pulse output (regardless of prescaler setting), then the pulse output will occur naturally and the counter will reset at the next prescaler counter naturally.
  3. In the event of a level-triggered Start/Reset, the active level must be asserted for at least one timer clock period to ensure proper sampling. If the duration of the asserted level is less than one timer clock, there is a possibility of the level trigger being missed and not sampled by the timer module.
Figure 28-8. Coincidental Start and Stop
Figure 28-9. ERS = 0 Level Reset
Figure 28-10. Rising Edge Start and Either Edge Stop
Figure 28-11. Reset at Level Start and Stop at PR Match