28.9.3 TUxyHLT

Hardware Limit Timer Control Register
Note:
  1. This bit is Reset to ‘1’.
  2. If CSYNC = 0, the ERS and ON edges must occur sufficiently further away from the clock edge to be registered into the timer domain. If the ERS and/or ON edges occur too close to the clock edge, it may result in a Race condition and the ERS/ON edges may be missed.
  3. The TUxyCLK clock source is enabled when ON = 1 regardless of the Start event.
  4. If EPOL = 1, then timer Start/Reset/Stop conditions happen at the alternate level/edge, respectively.
  5. When the timer is running, any subsequent Start condition is ignored. If RESET = ‘b10 (Reset at first clock after starting), the timer resets at every Start condition, even when the actual start event is being ignored.
  6. If START = ‘b11 (level triggered at ERS = 1), RESET = ‘b10 (Reset at first clock after starting) applies only at the Off-On transition of the timer’s Run state.
  7. If RESET = ‘b10 (level-triggered), the RUN bit is held at ‘0’.
  8. A Reset or Stop event reloads the PR register as described in Timer Period Register.
  9. Actions involving ERS require ON = 1 and a running clock.
  10. Software can always set ON = 0 to stop the counter.
  11. If OSEN = 1, a Stop event will clear ON.
  12. This register is not clock synchronized and needs to only be written when ON = 0.
  13. This register is not available when the module is chained and operated as a Secondary module.
Name: TUxyHLT

Bit 76543210 
 EPOLCSYNCSTART[1:0]RESET[1:0]STOP[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 01000000 

Bit 7 – EPOL ERS Polarity Selection

Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 The edges and levels for Start, Reset and Stop are inverted
0 The edges and levels for Start, Reset and Stop are the true input levels

Bit 6 – CSYNC  ERS Clock Synchronization Select(1,2)

Reset States: 
POR/BOR = 1
All Other Resets = u
ValueDescription
1 ERS and ON are synchronized with TUxyCLK
0 The counter starts, stops and resets asynchronously

Bits 5:4 – START[1:0]  Counter Start Condition Select(3,4)

Reset States: 
POR/BOR = 00
All Other Resets = uu
ValueDescription
11 Timer counter starts when ERS = 1
10 Timer counter starts at rising edge of ERS
01 Timer counter starts at either edge of ERS
00 No start due to ERS, timer runs when ON = 1

Bits 3:2 – RESET[1:0]  Counter Reset Condition Select(4,5,6,7,8)

Reset States: 
POR/BOR = 00
All Other Resets = uu
ValueDescription
11 Timer counter resets at PR match i.e., when counter equals PR; Next clock brings counter to zero
10 Timer counter resets at the first clock when starting and/or also at PR match
01 Timer counter resets when ERS = 0 and/or also at PR match
00 No hardware Reset

Bits 1:0 – STOP[1:0]  Counter Stop Condition Select(4,8,9,10,11)

The Stop feature has effect only when the counter is actively running. Once stopped, additional Stop events will not invoke capture or interrupt.
Reset States: 
POR/BOR = 00
All Other Resets = uu
ValueDescription
11 Timer stops counting at PR match i.e., when counter equals PR; current counter value is captured in TUxyCR
10 Timer stops counting at rising edge of ERS; current counter value is captured in TUxyCR
01 Timer stops counting at either edge of ERS; current counter value is captured in TUxyCR
00 ERS or PR match do not stop the timer; software must clear ON to stop the timer; current counter value is captured in TUxyCR at every rising edge of ERS
This bit is Reset to ‘1’. If CSYNC = 0, the ERS and ON edges must occur sufficiently further away from the clock edge to be registered into the timer domain. If the ERS and/or ON edges occur too close to the clock edge, it may result in a Race condition and the ERS/ON edges may be missed. The TUxyCLK clock source is enabled when ON = 1 regardless of the Start event. If EPOL = 1, then timer Start/Reset/Stop conditions happen at the alternate level/edge, respectively. When the timer is running, any subsequent Start condition is ignored. If RESET = ‘b10 (Reset at first clock after starting), the timer resets at every Start condition, even when the actual start event is being ignored. If START = ‘b11 (level triggered at ERS = 1), RESET = ‘b10 (Reset at first clock after starting) applies only at the Off-On transition of the timer’s Run state. If RESET = ‘b10 (level-triggered), the RUN bit is held at ‘0’. A Reset or Stop event reloads the PR register as described in Timer Period Register. Actions involving ERS require ON = 1 and a running clock. Software can always set ON = 0 to stop the counter. If OSEN = 1, a Stop event will clear ON. This register is not clock synchronized and needs to only be written when ON = 0. This register is not available when the module is chained and operated as a Secondary module.