8 Revision History

Revision	Date	Description
E	1/2022	In section Known Issues and Limitations, added Libero issue that if the keys in key Mode Policy are disabled and key Mode policy is used, the disabled keys can continue to be used to ERASE and VERIFY bitstreams.
D	11/2021	Added new section Standalone Synthesis Flow. In section Known Issues and Limitations, added a known issue about unused I/O pins glitching at power-up when Libero SoC-generated defaults are used.
C	09/2021	Added section Out-of-Context Derive Constraints Utility for Custom Flows. In section Known Issues and Limitations, added two SmartDebug issues: One about Data Rate, Link Width, and other values not appearing for a PCIe controller. One about designs using DDR controller with FHB enabled may crash.
B	08/2021	Editorial updates and bug fixes.
A	08/2021	Initial Revision

E

1/2022

In section Known Issues and Limitations, added Libero issue that if the keys in key Mode Policy are disabled and key Mode policy is used, the disabled keys can continue to be used to ERASE and VERIFY bitstreams.

D

11/2021

Added new section Standalone Synthesis Flow.
In section Known Issues and Limitations, added a known issue about unused I/O pins glitching at power-up when Libero SoC-generated defaults are used.

C

09/2021

Added section Out-of-Context Derive Constraints Utility for Custom Flows. In section Known Issues and Limitations, added two SmartDebug issues:

One about Data Rate, Link Width, and other values not appearing for a PCIe controller.
One about designs using DDR controller with FHB enabled may crash.

B

08/2021

Editorial updates and bug fixes.

A

08/2021

Initial Revision

Libero® SoC v2021.2

8 Revision History