1.3.9 Standalone Synthesis Flow

Libero SoC v2021.2 users can synthesize designs outside the Libero SoC software using Synopsys SynplifyPro directly. When using this flow, the following additional steps are necessary to synthesize and implement a design:

• For Windows, make sure the <install location>/Designer/data/aPA5M/polarfire_syn_comps.v is added as a source file to the SynplifyPro project. This file contains module declarations with timing information for PolarFire primitives not known to Synopsys.
• For Linux, make sure the <install location>/Libero/data/aPA5M/polarfire_syn_comps.v is added as a source file to the SynplifyPro project. This file contains module declarations with timing information for PolarFire primitives not known to Synopsys.
• Many configured cores generate timing constraints. For optimal results, make sure these constraint files are passed to synthesis. These constraint files must also be imported into Libero along with the synthesis gate level netlist for optimal place, route, and timing analysis results. Core-generated constraint files must be modified so that constraints are expressed using the proper hierarchical name of the configured cores in the top-level design.