1.2.5 SWI-PWM Interface
- SHA104 7-Bit Address 0x31 (Write 0x62, Read 0x63)
Parasitic Power
The SHA104 has the capability to use parasitic power on the SWI-PWM device. The Parasitic Power mode removes the need for a dedicated power source to the crypto device. Power is supplied to the device by capacitor C5. The capacitor is charged when SIO_2 (SIO-PWM mode) is higher than VCC_DVC. For proper operation, VCC_DVC must always be greater than the minimum supply operating voltage of the device. See the specific device data sheet for more details and recommendations. To enable Parasitic Power mode remove the JP1 Jumper cap from the JPP1 header.
For the EV97M19A, optional footprints are included for a 3-lead contact package version of the SHA104 and a 2-lead VSFN footprint for the SHA106 device. The SHA106 is a parasitic power-only version of the SHA104. The SHA106 includes an internal decoupling capacitor and is only available in a parasitic power mode. If so desired, the existing SHA104 can be removed from the board and either a 3-lead contact SHA104 or a SHA106 device can be added in its place. Note that the behavior of the devices are identical and any software developed for one of the devices will work with the other devices also.
The parasitic power boost circuitry is optional and is not populated on the EV97M19A development board. Information provided here is for completeness.
Follow these guidelines for proper circuitry usage:
- The device must be in Parasitic Power mode (remove jumper JPP1).
- The EPP# signal must be initially asserted HIGH.
- Issue a cryptography command.
- Assert the EPP# signal LOW for the duration of the command.
- Assert the EPP# signal HIGH.
- Read back the command response.
