Output Enable Timer Protection for GPIO Configuration

When the RESET Pin Configuration (RSTPINCFG) bit in FUSE.SYSCFG0 is ‘0x0’, the RESET pin is configured as GPIO. To avoid a potential conflict between the GPIO actively driving the output and a UPDI high-voltage (HV) enable sequence initiation, the GPIO output driver is disabled for a minimum of 8.8 ms after a System Reset.

It is always recommended to issue a Power-On Reset (POR) before entering the HV programming sequence.