1 SAM9x5 vs. SAM9X60 Feature Summary

The following table summarizes the differences between SAM9x5 and SAM9X60 features.

Table 1-1. SAM9x5 vs. SAM9X60 Features
Item	SAM9x5	SAM9X60	Comments
System
Core/Bus frequency	400/133 MHz	600/200 MHz	–
L1 cache size	16 Kbytes I + 16 Kbytes D	32 Kbytes I + 32 Kbytes D	–
SRAM size	32 Kbytes	64 Kbytes + 4 Kbytes for OTP emulation	–
OTP memory	–	11-Kbyte OTP Area for user’s certificates, keys and configuration Disable JTAG OTP bit Emulation mode (see SRAM)	23 Kbytes allocated to user
ROM boot	No security/encryption features	Secure boot with encryption, certificates and key management (see OTP)	–
Power supplies	1.0V core voltage	1.1V core voltage 2.5V regulator added VDDQSPI segment	For PLLs and oscillators
System controller, clocks, power management	32 KHz RC can be stopped 12 to 16 MHz crystal 12 MHz required for USB operations 400 to 800 MHz PLLs Peripheral I/Os are clocked at MCK	32 KHz RC always on 12 to 48 MHz crystal Main RC calibration 32 KHz RC calibration More frequencies can fit USB operation; PLLs are fractional 600 to 1200 MHz PLLs with spread spectrum Generic clocks available for most peripheral I/Os Clocks monitoring ULP1 added, power consumption improved and wake-up time reduced Separated pins for reset input (NRST) and reset output (NRST_OUT)	Safety for WDT, RSTC, etc. EMI/EMC improvement
DMA	2x 8-channel DMAs	1x 16-channel DMA	–
DDR controller	External resistors needed for PCB impedance matching	DDR I/Os with calibration for impedance matching, additional control signal	Reduced BOM cost and board space
NAND Flash	16-bit	8-bit only	–
Special Function Register	Memory mapped in Matrix section	Memory mapped in SFR section	–
Peripheral Multiplexing on I/O lines	–	Compatible 7 lines added Peripherals added	–
Peripheral Upgrades
eMMC	HSMCI, eMMC 4.1	SDMMC, eMMC 4.51
Serial	USART0-2 SPI0-1 TWI0-2 UART0-1	FLEXCOM0-2 FLEXCOM4-5^() FLEXCOM6-8 FLEXCOM9-10 FLEXCOM3-11-12 added ^()Some FLEXCOMs include extra IOSETs.	Some FLEXCOMs enable USART, SPI and TWI functions, or only UART and TWI
USB	2x HS + 1x FS transceivers 4-Kbyte DPRAM with dynamic allocation	3x HS transceivers External Full Speed resistors removed 16-Kbyte DPRAM; each end point has its own memory area	–
Soft Modem (SMD)	Embedded	Removed	–
LCD controller	4 layers: Base Overlay High end HW cursor 800x600 pixel resolution	4 layers: Base Overlay1 Overlay2 High end 1024x768 pixel resolution	–
2D graphics (GFX2D)	–	Added	–
ADC	10 bits	12 bits Internal triggers	–
64-bit Timer (PIT64B)	–	Added	–
QSPI	–	4-bit QSPI added with dedicated power supply	SDR and DDR support; eXecution In Place (XIP)
I2SMCC	–	Added	–
CLASSD	–	Added	–
Encryption engines (TDES, AES, SHA, TRNG)	–	Added	–
Packages	BGA217, 15x15 mm², 0.8 mm pitch BGA247, 10x10 mm², 0.5 mm pitch	BGA196 11x11 mm² 0.65 mm pitch for SiP with 64-Mbit SDRAM BGA228, 11x11 mm², 0.65 mm pitch BGA233 14x14 mm² 0.8 mm pitch for SiP with 512-Mbit and 1-Gbit DDR2 SDR-SDRAM and DDR2-SDRAM SiP added	Accommodates 4-layer PCBs