11.4.2 Natural Order (Hardware) Priority

When vectored interrupts are enabled and more than one interrupt with the same user specified priority level is requested, the priority conflict is resolved by using a method called “Natural Order Priority”. Natural order priority is a fixed priority scheme that is based on the IVT.

Table 11-2. Interrupt Vector Priority Table
Vector

Number

Interrupt

source

Vector

Number

(cont.)

Interrupt

source

(cont.)

0x0Software Interrupt0x2DCLC2
0x1HLVD (High/Low-Voltage Detect)0x2EPWM2PR
0x2OSF (Oscillator Fail)0x2FPWM2
0x3CSW (Clock Switching)0x30INT1
0x4NVM0x31CWG1 (Complementary Waveform Generator)
0x5CLC1 (Configurable Logic Cell)0x32NCO1 (Numerically Controlled Oscillator)
0x6CRC (Cyclic Redundancy Check)0x33DMA2SCNT
0x7IOC (Interrupt-On-Change)0x34DMA2DCNT
0x8INT00x35DMA2OR
0x9ZCD (Zero-Cross Detection)0x36DMA2A
0xAAD (ADC Conversion Complete)0x37-
0xBACT (Active Clock Tuning)0x38I2C1RX
0xCCM1 (Comparator)0x39I2C1TX
0xDSMT1 (Signal Measurement Timer)0x3AI2C1
0xE-0x3BI2C1E
0xFSMT1PWA0x3C-
0x10ADT0x3DCLC3
0x11 - 0x13-0x3EPWM3PR
0x14DMA1SCNT (Direct Memory Access)0x3FPWM3
0x15DMA1DCNT0x40U2RX
0x16DMA1OR0x41U2TX
0x17DMA1A0x42U2E
0x18SPI1RX (Serial Peripheral Interface)0x43U2
0x19SPI1TX0x44-
0x1ASPI10x45CLC4
0x1BTMR20x46-
0x1CTMR10x47SCAN
0x1DTMR1G0x48U3RX
0x1ECCP1 (Capture/Compare/PWM)0x49U3TX
0x1FTMR00x4AU3E
0x20U1RX0x4BU3
0x21U1TX0x4CDMA3SCNT
0x22U1E0x4DDMA3DCNT
0x23U10x4EDMA3OR
0x24TMR30x4FDMA3A
0x25TMR3G0x50INT2
0x26PWM1PR0x51-
0x27PWM10x52-
0x28SPI2RX0x53TMR4
0x29SPI2TX0x54DMA4SCNT
0x2ASPI20x55DMA4DCNT
0x2B-0x56DMA4OR
0x2CCM2 (Comparator)0x57DMA4A

The natural order priority scheme goes from high-to-low with increasing vector numbers, with 0 being the highest priority and decreasing from there.

For example, when two concurrently occurring interrupt sources that are both designated high priority, using the IPRx register will be resolved using the natural order priority (i.e., the interrupt with a lower corresponding vector number will preempt the interrupt with the higher vector number).

The ability for the user to assign every interrupt source to high- or low-priority levels means that the user program can give an interrupt with a low natural priority, a higher overall priority level.