8.5 Atmel AVR UC3 OCD

JTAG interface

On some Atmel AVR UC3 microcontrollers the JTAG port is not enabled by default. When using these devices it is essential to connect the RESET line so that the Atmel AVR JTAGICE mkII can enable the JTAG interface.

Any stabilizing capacitor connected to the RESET pin must be disconnected when using aWire since it will interfere with correct operation of the interface. A weak external pullup on this line is recommended.

aWire interface

The baud rate of aWire communications depends upon the frequency of the system clock, since data must be synchronized between these two domains. The JTAGICE mkII will automatically detect that the system clock has been lowered, and re-calibrate its baud rate accordingly. The automatic calibration only works down to a system clock frequency of 8kHz. Switching to a lower system clock during a debug session may cause contact with the target to be lost.

If required, the aWire baud rate can be restricted by setting the aWire clock parameter in the tool-chain. Automatic detection will still work, but a ceiling value will be imposed on the results.

Shutdown sleep mode

Some AVR UC3 devices have an internal regulator that can be used in 3.3V supply mode with 1.8V regulated I/O lines. This means that the internal regulator powers both the core and most of the I/O. The JTAGICE mkII does not support the Shutdown sleep mode were this regulator is shut off. In other words this sleep mode cannot be used during debugging. If it is a requirement to use this sleep mode during debugging, use an Atmel AVR ONE! debugger instead.