2.4.1 Two UPDI Low Pulses in Quick Succession Can Cause Increased Power Consumption

If the second UPDI low pulse occurs less than 20 ms after the first pulse and has a duration of more than 4 ms, the UPDI clock may continue running after the second pulse is complete. This will lead to increased power consumption, and the programming and debugging interface will remain disabled.

Work Around

On the UPDI pin, avoid low pulses and glitches with intervals of less than 20 ms between them.

Affected Silicon Revisions


A0
X

DS80001125D

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