1 AVR 8-bit Architecture

The AVR architecture is based upon the Harvard architecture. It has separate memories and buses for program and data. This makes it possible to fetch program and data simultaneously. It has 32 8-bit fast-access General Purpose Working Registers with a single clock cycle access time. The 32 working registers is one of the keys to efficient C coding. The registers are connected to the ALU so arithmetic and logical instructions can be performed on the data in these registers. In one clock cycle, an AVR can feed data from two arbitrary registers to the ALU, perform an operation, and write back the result to the registers.

Instructions in the program memory are executed with a single level pipeline. While one instruction is being executed, the next instruction is fetched from the program memory. This concept enables instructions to be executed in every clock cycle. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Refer to the “AVR CPU Core” section in the respective device datasheet for more details.