25.1 SPI Mode Overview

The Serial Peripheral Interface (SPI) is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a host/client environment where the host device initiates the communication. A client device is selected for communication using the Client Select feature.

The SPI bus specifies four signal connections:

  • Serial Clock (SCK)
  • Serial Data Out (SDO)
  • Serial Data In (SDI)
  • Client Select (SS)

Figure 25-1 shows the block diagram of the MSSP module when operating in SPI mode.

Figure 25-1. MSSP Block Diagram (SPI Mode)

The SPI bus operates with a single host device and one or more client devices. When multiple client devices are used, an independent Client Select connection is required from the host device to each client device. The host selects only one client at a time. Most client devices have tri-state outputs, so their output signal appears disconnected from the bus when they are not selected.

Figure 25-2 shows a typical connection between a host device and multiple client devices.

Figure 25-2. SPI Host and Multiple Client Connection

Transmissions involve two shift registers, eight bits in size: One in the host and one in the client. Data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register.

Figure 25-3 shows a typical connection between two processors configured as host and client devices.

Figure 25-3. SPI Host/Client Connection

Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock.

The host device transmits information out on its SDO output pin, which is connected to and received by the client’s SDI input pin. The client device transmits information out on its SDO output pin, which is connected to and received by the host’s SDI input pin.

To begin communication, the host device transmits both the MSb from its shift register and the clock signal. Both the host and client devices need to be configured for the same clock polarity. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the host device is sending out the MSb from its shift register (on its SDO pin) and the client device is reading this bit and saving it as the LSb of its shift register, the client device is also sending out the MSb from its shift register (on its SDO pin) and the host device is reading this bit and saving it as the LSb of its shift register.

After eight bits have been shifted out, the host and client have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data) depends on the application software. This leads to three scenarios for data transmission:

  • Host sends useful data and client sends dummy data.
  • Host sends useful data and client sends useful data.
  • Host sends dummy data and client sends useful data.

Transmissions must be performed in multiples of eight clock cycles. When there is no more data to be transmitted, the host stops sending the clock signal and it deselects the client.

Every client device connected to the bus that has not been selected through its Client Select line must disregard the clock and transmission signals and must not transmit out any data of its own.