12.9.7 PIR2

Peripheral Interrupt Request Register 2
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable (GIE) bit. User software needs to ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: PIR2
Offset: 0x70E

Bit 76543210 
 CCP2IFNVMIFTMR1GIF      
Access R/W/HSR/W/HSR/W/HS 
Reset 000 

Bit 7 – CCP2IF CCP2 Interrupt Flag

ValueCCP Mode
CaptureComparePWM
1Capture occurred (must be cleared in software)Compare match occurred (must be cleared in software)Output trailing edge occurred (must be cleared in software)
0Capture did not occurCompare match did not occurOutput trailing edge did not occur

Bit 6 – NVMIF Nonvolatile Memory (NVM) Interrupt Flag

ValueDescription
1The requested NVM operation has completed (must be cleared in software)
0Interrupt event has not occurred

Bit 5 – TMR1GIF TMR1 Gate Interrupt Flag

ValueDescription
1The TMR1 Gate has gone inactive (must be cleared in software)
0TMR1 Gate is active
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable (GIE) bit. User software needs to ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.