33.5.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | CONVMODE | LEFTADJ | RESSEL[1:0] | FREERUN | ENABLE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – RUNSTDBY Run in Standby
This bit determines whether the ADC still runs during Standby.
| Value | Description |
|---|---|
| 0 | ADC will not run in Standby sleep mode. An ongoing conversion will finish before the ADC enters sleep mode. |
| 1 | ADC will run in Standby sleep mode |
Bit 5 – CONVMODE Conversion Mode
This bit defines if the ADC is working in Single-Ended or Differential mode.
| Value | Name | Description |
|---|---|---|
| 0x0 | SINGLEENDED | The ADC is operating in Single-Ended mode where only the positive input is used. The ADC result is presented as an unsigned value. |
| 0x1 | DIFF | The ADC is operating in Differential mode where both positive and negative inputs are used. The ADC result is presented as a signed value. |
Bit 4 – LEFTADJ Left Adjust Result
1’ to this bit will enable left adjustment of the ADC
result.Bits 3:2 – RESSEL[1:0] Resolution Selection
This bit field selects the ADC resolution. When changing the resolution from 12-bit to 10-bit, the conversion time is reduced from 13.5 CLK_ADC cycles to 11.5 CLK_ADC cycles.
| Value | Description |
|---|---|
| 0x00 | 12-bit resolution |
| 0x01 | 10-bit resolution |
| Other | Reserved |
Bit 1 – FREERUN Free-Running
Writing a ‘1’ to this bit will enable the
Free-Running mode for the ADC. The first conversion is started by writing a
‘1’ to the Start Conversion (STCONV) bit in the Command
(ADCn.COMMAND) register.
Bit 0 – ENABLE ADC Enable
| Value | Description |
|---|---|
| 0 | ADC is disabled |
| 1 | ADC is enabled |