27.5.9 Control C - Host SPI Mode

This register description is valid only when the USART is in Host SPI mode (CMODE written to MSPI). For other CMODE values, see CTRLC - Normal Mode.

See 27.3.3.1.3 USART in Host SPI Mode for a full description of the Host SPI mode operation.

Name: CTRLC
Offset: 0x07
Reset: 0x00
Property: -

Bit 76543210 
 CMODE[1:0]   UDORDUCPHA  
Access R/WR/WR/WR/W 
Reset 0000 

Bits 7:6 – CMODE[1:0] USART Communication Mode

This bit field selects the communication mode of the USART.

Writing a value different than 0x03 to these bits alters the available bit fields in this register. See CTRLC - Normal Mode.

ValueNameDescription
0x00ASYNCHRONOUSAsynchronous USART
0x01SYNCHRONOUSSynchronous USART
0x02IRCOMInfrared Communication
0x03MSPIHost SPI

Bit 2 – UDORD USART Data Order

This bit controls the frame format. The receiver and transmitter use the same setting. Changing the setting of the UDORD bit will corrupt all ongoing communication for both the receiver and the transmitter.

ValueDescription
0MSb of the data word is transmitted first
1LSb of the data word is transmitted first

Bit 1 – UCPHA USART Clock Phase

This bit controls the phase of the interface clock. Refer to the 27.3.3.1.3.2 Clock Generation section for more information.

ValueDescription
0Data are sampled on the leading (first) edge
1Data are sampled on the trailing (last) edge