6 Frequency Deviation

PLC communications, based on OFDM, requires a clock synchronization on devices to fulfill with physical requirements implicit to the technology. This topic addresses the process of analysis of this requirement.

The Microchip PLC Frequency Deviation Python script tool requirements are as follows:
  • The PLC device in reception runs the PHY Tester tool embedded project included in the Microchip PLC firmware package.
  • Primed to process a received frame every second, which will subsequently update a histogram (see Figure 6-1) that illustrates the discrepancy in frequency deviation between devices.
Figure 6-1. Microchip PLC Frequency Deviation Test – Measurement
The scenario of testing is shown in Figure 6-2.
Figure 6-2. Microchip PLC Frequency Deviation Test – Measurement Setup
It requires a tester device calibrated in frequency acting like transmitter controlled with the PHY Tester Tool with a configuration where the time between frames is higher than 1 second (Figure 6-3) and the receiver DUT about which the PLC Frequency Deviation tool acts.
Figure 6-3. Microchip PLC Frequency Deviation Test – PLC PHY Tester Tool TX Configuration

According to the G3-PLC specification, the imperfection of the sampling clock frequency variation can cause inter-carrier interference (ICI). In practice, the ICI caused by a typical sampling frequency variation of about 2% of the frequency spacing is negligible. In other words, considering a ±25 ppm sampling frequency in the transmitter and receiver clocks, the drift of the subcarriers is approximately equal to 8 Hz, that is approximately 0.5% of the selected frequency spacing. Considering these selections, the number of usable subcarriers is set to 36 for the CENELEC-A band, 16 for the CENELEC-B band and 72 for the FCC band.

The system clock frequency tolerance is +/-25 ppm maximum and the transmit frequency and symbol timing is derived from the same system clock oscillator. As this tolerance must be accomplished on the full temperature range of use for the device, a good criteria in testing is to measure the frequency deviation in both extremes of the temperature range.

The worst case analyzing the frequency deviation in reception is with Coherent ROBO frames with the maximum length on the frequency band with the full tone masking/mapping including CRC (2 bytes). An indirect way to find this kind of problems in frequency deviation appear when running certification performance tests that use coherent modulations evaluating the device in reception.

Important: According to the PRIME specification, the system clock shall have a maximum tolerance of +/-50 ppm, including ageing.
Tip: Follow the process of crystal selection and hardware configuration by reading the Microchip Application Note AN2716 – Crystal Selection Guidelines for PLC Devices.
The main purpose of Frequency Deviation tool are:
  • To tune the capacitors selected for the crystal configuring a PIN of the PLC device as clock output of the internal 24Mhz signal to be analyzed with an oscilloscope or spectrum analyzer.
  • To identify the frequency deviation between devices analyzing the received frames.
The Frequency Deviation tool use the following PIBs to recover the information:
  • REG_PPM_CALIB_ON: Enable the oscillator clock signal to go out through the TXRX1 pad.
  • REG_SFO_ESTIMATION_LAST_RX: Estimation of the clock frequency deviation on the last received PDU.
Important: For more information about those PIBs, refer to the Microchip PL360 Host Controller User Guide.
To use the tool just follow these steps:
  1. Mount the 24 MHz clock crystal capacitors according to the Microchip reference design and guidelines followed on the crystal selection application note.
  2. Configure the device with the firmware project phy_tester_tool.
  3. Run the PLCFreqDev tool or Python script.
  4. Configure the Serial Port and the Baudrate for connecting to the board (push the Refresh button, if necessary, for updating the serial ports available).
    Figure 6-4. Microchip PLC Frequency Deviation Test – Connection
  5. Push the Connect button for accessing the board. The Device Info layout is updated with information from the firmware.
    Figure 6-5. Microchip PLC Frequency Deviation Test – Device Info
  6. Now depending of the purpose to use the tool:
    • To calibrate the frequency clock source: press the EnClockOut button that enables the availability of the PLC module reference clock signal on the TXRX1 pad (24 MHz). The clock frequency can be adjusted by modifying the values of the associated capacitors as explained in the application note Crystal Selection Guidelines. It is recommended to tune the tester board to be as close as possible to 24MHz because the frequency deviation is a differential measurement between receiver and transmitter.
    • To analyze the frequency deviation: press the MeasFreqDev button that starts the application obtaining the frequency deviation from received frames inside the PLC module and showing the histogram with a maximum refresh of 1 second.
The results can be analyzed according the table Table 6-1.
Table 6-1. PLC Frequency Deviation Measurement Results
Absolute Frequency Deviation Meas RANGE (ppm)RESULT
<= 10VERY GOOD
10 < FreqDevMeas <= 20GOOD
20 < FreqDevMeas <= 25POOR
>25POTENTIAL ISSUES