2.8 d8: Table 7-15. RMII Timing

The minimum guaranteed RMII setup timing is reduced to 2 ns. Replace Table 7-15 in section 7.6.7 with the following updated table.

Table 7-15. RMII Timing


Description	Symbol	Min	Typ	Max	Units	Additional Information
REFCLKIN period	t_clkp		20		ns	Note 1
REFCLKIN high time	t_clkh	t_clkp* 0.45		t_clkp* 0.55	ns	Note 1, 2
REFCLKIN low time	t_clkl	t_clkp* 0.45		t_clkp* 0.55	ns	Notes 1, 2
RXD[1:0], RXER, CRSDV output valid from rising edge of REFCLKIN	t_oval			12	ns
RXD[1:0], RXER, CRSDV output invalid from rising edge of REFCLKIN	t_oinvld	3.0			ns
TXD[1:0], TXEN setup time to rising edge of REFCLKIN	t_su	2.0			ns
TXD[1:0], TXEN hold time after rising edge of REFCLKIN	t_ihold	1.5			ns
Note: Design parameter, not tested. 1.8V 50 MHz clock input on REFCLKIN