20.5.11 Interrupt Flag Register - Normal Mode

The individual Status bit can be cleared by writing a '1' to its bit location. This allows each bit to be set without the use of a read-modify-write operation on a single register.
Name: INTFLAGS
Offset: 0x0B
Reset: 0x00
Property: -

Bit 76543210 
  CMP2CMP1CMP0   OVF 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 6 – CMP2 Compare Channel 2 Interrupt Flag

See CMP0 flag description.

Bit 5 – CMP1 Compare Channel 1 Interrupt Flag

See CMP0 flag description.

Bit 4 – CMP0 Compare Channel 0 Interrupt Flag

The Compare Interrupt flag (CMPn) is set on a compare match on the corresponding compare channel.

For all modes of operation, the CMPn flag will be set when a compare match occurs between the Count register (TCAn.CNT) and the corresponding Compare register (TCAn.CMPn). The CMPn flag is not cleared automatically, only by writing a ‘1’ to its bit location.

Bit 0 – OVF Overflow/Underflow Interrupt Flag

This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting. The OVF flag is not cleared automatically, only by writing a ‘1’ to its bit location.