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tinyAVR® 1-series ATtiny1617/3217
Introduction
Features
1 Silicon Errata and Data Sheet Clarification Document
2 tinyAVR® 1-series Overview
2.1 Configuration Summary
3 Block Diagram
4 Pinout
4.1 24-Pin VQFN
5 I/O Multiplexing and Considerations
5.1 Multiplexed Signals
6 Memories
6.1 Overview
6.2 Memory Map
6.3 In-System Reprogrammable Flash Program Memory
6.4 SRAM Data Memory
6.5 EEPROM Data Memory
6.6 User Row
6.7 Signature Bytes
6.8 I/O Memory
6.9 Memory Section Access from CPU and UPDI on Locked Device
6.10 Configuration and User Fuses (FUSE)
7 Peripherals and Architecture
7.1 Peripheral Module Address Map
7.2 Interrupt Vector Mapping
7.3 System Configuration (SYSCFG)
8 AVR CPU
8.1 Features
8.2 Overview
8.3 Architecture
8.4 Arithmetic Logic Unit (ALU)
8.5 Functional Description
8.6 Register Summary - CPU
8.7 Register Description
9 NVMCTRL - Nonvolatile Memory Controller
9.1 Features
9.2 Overview
9.3 Functional Description
9.4 Register Summary - NVMCTRL
9.5 Register Description
10 CLKCTRL - Clock Controller
10.1 Features
10.2 Overview
10.3 Functional Description
10.4 Register Summary - CLKCTRL
10.5 Register Description
11 SLPCTRL - Sleep Controller
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Register Summary - SLPCTRL
11.5 Register Description
12 RSTCTRL - Reset Controller
12.1 Features
12.2 Overview
12.3 Functional Description
12.4 Register Summary - RSTCTRL
12.5 Register Description
13 CPUINT - CPU Interrupt Controller
13.1 Features
13.2 Overview
13.3 Functional Description
13.4 Register Summary - CPUINT
13.5 Register Description
14 EVSYS - Event System
14.1 Features
14.2 Overview
14.3 Functional Description
14.4 Register Summary - EVSYS
14.5 Register Description
15 PORTMUX - Port Multiplexer
15.1 Overview
15.2 Register Summary - PORTMUX
15.3 Register Description
16 PORT - I/O Pin Configuration
16.1 Features
16.2 Overview
16.3 Functional Description
16.4 Register Summary - PORT
16.5 Register Description - Ports
16.6 Register Summary - VPORT
16.7 Register Description - Virtual Ports
17 BOD - Brown-out Detector
17.1 Features
17.2 Overview
17.3 Functional Description
17.4 Register Summary - BOD
17.5 Register Description
18 VREF - Voltage Reference
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary - VREF
18.5 Register Description
19 WDT - Watchdog Timer
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Register Summary - WDT
19.5 Register Description
20 TCA - 16-bit Timer/Counter Type A
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary - TCA in Normal Mode (CTRLD.SPLITM=0)
20.5 Register Description - Normal Mode
20.6 Register Summary - TCA in Split Mode (CTRLD.SPLITM=1)
20.7 Register Description - Split Mode
21 TCB - 16-bit Timer/Counter Type B
21.1 Features
21.2 Overview
21.3 Functional Description
21.4 Register Summary - TCB
21.5 Register Description
22 TCD - 12-Bit Timer/Counter Type D
22.1 Features
22.2 Overview
22.3 Functional Description
22.4 Register Summary - TCD
22.5 Register Description
23 RTC - Real-Time Counter
23.1 Features
23.2 Overview
23.3 RTC Functional Description
23.4 PIT Functional Description
23.5 Events
23.6 Interrupts
23.7 Sleep Mode Operation
23.8 Synchronization
23.9 Configuration Change Protection
23.10 Register Summary - RTC
23.11 Register Description
24 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
24.1 Features
24.2 Overview
24.3 Functional Description
24.4 Register Summary - USART
24.5 Register Description
25 SPI - Serial Peripheral Interface
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary - SPI
25.5 Register Description
26 TWI - Two-Wire Interface
26.1 Features
26.2 Overview
26.3 Functional Description
26.4 Register Summary - TWI
26.5 Register Description
27 CRCSCAN - Cyclic Redundancy Check Memory Scan
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary - CRCSCAN
27.5 Register Description
28 CCL - Configurable Custom Logic
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary - CCL
28.5 Register Description
29 AC - Analog Comparator
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary - AC
29.5 Register Description
30 ADC - Analog-to-Digital Converter
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary - ADCn
30.5 Register Description
31 DAC - Digital-to-Analog Converter
31.1 Features
31.2 Overview
31.3 Functional Description
31.4 Register Summary - DAC
31.5 Register Description
32 Peripheral Touch Controller (PTC)
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 Signal Description
32.5 System Dependencies
32.6 Functional Description
33 UPDI - Unified Program and Debug Interface
33.1 Features
33.2 Overview
33.3 Functional Description
33.4 Register Summary - UPDI
33.5 Register Description
34 Instruction Set Summary
35 Conventions
35.1 Numerical Notation
35.2 Memory Size and Type
35.3 Frequency and Time
35.4 Registers and Bits
36 Acronyms and Abbreviations
37 Electrical Characteristics
37.1 Disclaimer
37.2 Absolute Maximum Ratings
37.3 General Operating Ratings
37.4 Power Consumption for ATtiny1617
37.5 Power Consumption for ATtiny3217
37.6 Wake-Up Time
37.7 Power Consumption of Peripherals
37.8 BOD and POR Characteristics
37.9 External Reset Characteristics
37.10 Oscillators and Clocks
37.11 I/O Pin Characteristics
37.12 USART
37.13 SPI
37.14 TWI
37.15 VREF
37.16 ADC
37.17 DAC
37.18 AC
37.19 PTC
37.20 UPDI Timing
37.21 Programming Time
38 Typical Characteristics
38.1 Power Consumption
38.2 GPIO
38.3 VREF Characteristics
38.4 BOD Characteristics
38.5 ADC Characteristics
38.6 AC Characteristics
38.7 OSC20M Characteristics
38.8 OSCULP32K Characteristics
39 Ordering Information
39.1 Product Information
39.2 Product Identification System
40 Package Drawings
40.1 Online Package Drawings
40.2 24-Pin VQFN
41 Thermal Considerations
41.1 Thermal Resistance Data
41.2 Junction Temperature
42 Errata
42.1 Errata - ATtiny1617/3217
43 Data Sheet Revision History
43.1 Rev. C - 07/2019
43.2 Rev. B - 06/2018
43.3 Rev. A - 06/2018
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