1.1 Features

  • Arm Cortex-A7 Core
    • Arm TrustZone®
    • Arm® Neon™ multimedia architecture
    • Floating Point Unit
    • Embedded Trace module with instruction trace stream, including 16 Kbytes of CoreSight™ Embedded Trace buffer
    • 32 Kbytes of L1 data cache, 32 Kbytes of L1 instruction cache
    • 256 Kbytes of L2 cache
    • Up to 1 GHz operational frequency
    • Voltage and frequency scaling support
    • 64-bit generic timers
  • Memories
    • Internal memory architecture
      • 128 Kbytes of SRAM
      • 80 Kbytes of ROM, embedding a secure boot loader (boot on QSPI NOR, SLC/MLC NAND, SD card, e.MMC)
      • 96 Kbytes ROM for NAND Flash ECC tables
      • 40 Kbytes ROM for crypto libraries (RSA, ECC, etc.)
      • 11 Kbytes of internal OTP
    • External memory support
      • 16-bit high-bandwidth, Double Data Rate Multi-Port Dynamic RAM controller. Supports up to 16 Gbit 8-bank DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 up to 533 MHz
      • 16-bit Static Memory controller, FPGA and memory-mapped peripheral support with synchronous clock
  • System
    • Power-on reset cells, reset controller, shutdown controller, watchdog and secure watchdog timers running on internal slow RC oscillator (32 kHz typical) and real-time clock running on slow crystal oscillator (32.768 kHz)
    • Two internal trimmed RC oscillators with typical values: 32 kHz and 12 MHz
    • Two crystal oscillators: 32.768 kHz and 20 to 50 MHz
    • Nine PLLs for core, system bus and peripherals, serial interfaces, DDR I/Os, pixel clock, audio, USB and Ethernet
    • Two 32-channel DMA with per-channel security configuration
    • One 8-channel DMA dedicated to memory-to-memory transactions
    • Eight programmable clock output signals
  • Power Considerations
    • Different power domains and power modes to reduce power consumption
    • Low-power consumption in Backup mode with 5 Kbytes of secure backup SRAM and DDR-SDRAM in Self-Refresh mode
    • Low-power with SRAM and register retention, wake-up from various events (USB, CAN, Ethernet WOL, FLEXCOMs), internal events (RTC, timer) and I/O activity
    • Embedded LDOs for analog and PLLs to enable low-cost power management solutions
    • Optimum connection to Microchip MCP16501/2 PMICs to enter and exit various power modes of the application
  • Multimedia Peripherals
    • Audio
      • Two synchronous serial controllers, each with up to eight channels of up to 32-bit TDM data
      • Two inter-IC sound multi-channel controller with TDM256 support
      • Up to two 4-channel pulse density microphone controllers; support for eight microphones in parallel
      • One Sony/Philips Digital Interface transmitter and receiver
      • Audio sample rate converter including four stereo channels
  • Display Subsystem Supporting One Display Up to WXGA/720p (1366x768p60/1280x720p60)
    • One 4-lane MIPI D-PHY interface and one DSI controller
    • One single-channel LVDS interface, and one LVDS controller
    • 8-bit databus serial RGB interface
    • One LCD controller with one base layer, one overlay and one high-end overlay
    • One 2D GPU controller with up to WXGA/720p target display resolution and support for RGB and YUV
  • Connectivity
    • USB Subsystem:
      • Two high-speed USB Devices and three high-speed USB Hosts sharing three on-chip transceivers
      • Two USB Type-C™ controllers (TCPC)
    • Two 10/100/1000 Gigabit Ethernet MAC supporting:
      • RGMII and RMII interfaces
      • Energy efficiency as per IEEE 802.3az
      • Ethernet AVB support with IEEE802.1AS timestamping
      • IEEE802.1Qav credit-based traffic shaping hardware support
      • IEEE1588 Precision Time Protocol
      • IEEE1588 Timestamp Unit with TSU timer comparison signal triggering a Timer Counter and available on a PIO line
      • Support for traffic scheduling and Time Sensitive Networking (TSN/AVB)
      • Packet buffer support
    • Five flexible data rate CAN-FD controllers with SRAM-based mailboxes with time- and event-triggered transmission, flexible data rate. 32-bit Timestamp unit.
    • Eleven FLEXCOMs supporting U(S)ART, SPI, TWI/I2C with FIFOs
    • I3C controller interface supporting FM, FM+, SDR and HDR-DDR modes
  • Mass Storage
    • One 8-bit high-speed Memory Card Host with e.MMC 5.1 (HS400), SD3.0, SDR104 mode support
    • One 4-bit high-speed Memory Card Host with e.MMC 5.1 (HS200), SD3.0, SDR104 mode support
    • One 4-bit high-speed Memory Card Host with SD3.0, SDR104 mode support
    • One Octal Serial Peripheral Interface supporting high-speed DDR mode
    • One Quad Serial Peripheral Interface
    • 8-bit SLC and MLC NAND controller with up to 32-bit Error Correcting Code
  • General-Purpose Analog and Digital Peripherals
    • Six 64-bit Periodic Interval Timers
    • Two three-channel 32-bit Timer Counters with PWM generation
    • One four-channel 16-bit PWM controller
    • One 19-channel 12-bit 1 Msps Analog-to-Digital converter
    • One 4-differential inputs Analog Comparator controller
  • Safety
    • Zero-power power-on reset cells
    • Main crystal monitor and clock failure detector with failsafe switchover to Main RC oscillator
    • 32 kHz crystal monitor and clock failure detector, switch to internal 32 kHz RC
    • Integrity Check Monitor based on SHA256
    • One Watchdog Timer running on RC oscillator
    • Register write protection
  • Security
    • TrustZone support
    • One Secure TrustZone Watchdog Timer running on RC oscillator, providing protection against TrustZone starvation
    • Temperature, voltage and frequency monitoring (also applicable for safety purposes)
    • Secure backup SRAM
      • 5 Kbytes scrambled with non-imprinting support powered with VBAT or VDDIN33:
        • 1 Kbyte non-erasable on tamper detection
        • 4 Kbytes erasable on tamper detection
    • Four tamper pins for static or dynamic detection
      • Can be used as regular wake-up lines
    • 256-bit backup register, erasable on tamper detection (tamper pins or monitor outputs). Time Stamping of tamper events.
    • Programmable OTP with bits available for user purposes
    • Configurable JTAG/SWD security (full debug, Non-secure-only debug, no debug)
    • Two independent 128-bit AES on-the-fly encryption/decryption on DDR memory, SMC, QSPI0 and QSPI1, including automatic key load at start-up. Separate key for Secure and Non-secure accesses (TZAESB)
    • Secure RTC
  • Cryptography
    • Physically Unclonable Function with automatic key load to hardware encryption engines
    • SHA (SHA1, SHA224, SHA256, SHA384, SHA512) compliant with FIPS Publications 180-2
    • AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197 specifications
    • TDES: Two-key or three-key algorithms, compliant with FIPS PUB 46-3 specifications
    • True Random Number Generator with health tests compliant with NIST Special Publication 800-22 Tests Suite and FIPS PUB 140-2 and 140-3
    • Public Key Coprocessor (CPKCC) and associated Classical Public Key Cryptography Library (CPKCL) for RSA, DSA, ECC GF(2n), ECC GF(p) (1) and associated library for RSA4096, ECC521.
  • I/O Ports
    • Up to 142 general-purpose I/Os
    • Fully programmable through Set/Clear registers
    • Multiplexing of up to eight peripheral functions per I/O line
    • Each I/O line can be assigned to a peripheral or used as a general-purpose I/O
    • Synchronous output, possibility to set or clear simultaneously up to 32 I/O lines in a single write
    • General-purpose analog and digital inputs are tolerant to positive and negative current injection
  • Design for Low Electromagnetic Interference (EMI)
    • Slew rate controlled I/Os
    • DDR Phy with impedance-calibrated drivers
    • Programmable spread spectrum PLLs
    • Careful BGA power/ground ball assignment to provide optimum decoupling capacitors placement
  • Microchip Recommended Power Management Integrated Circuits (PMICs)
    • MCP16502, 6-channel PMIC with I²C control interface; supports dynamic voltage scaling and processor Low-Power modes (BSR)
    • MCP16501, 4-channel PMIC optimized for compact PCB layout; supports processor Low-Power mode (BSR)
  • Operating Conditions
    • Junction temperature range (TJ): Industrial (-40°C to +105°C)
  • Package
    • 343-ball BGA 14x14x1.2 mm, 0.65 mm pitch, optimized for standard class PCB layout (down to 4 layers)
Note:

  1. Public Key Coprocessor (CPKCC) and associated Classical Public Key Cryptography Library (CPKCL) are described in the application note "Using CPKCL Version 02.11.01.xx on SAMA7D65" (AN5646). This document is available under Non-Disclosure Agreement (NDA). Contact a Microchip Sales Representative for further details.