9.3.2.3 TWI/SMBus Characteristics

  • 32-byte Transmit and Receive FIFOs
  • Bit Rate can be Independent of the Processor/Peripheral Clock
  • SMBus Support
  • Compatible with I2C Compatible Devices(1)
  • One, Two or Three Bytes for Client Address
  • Sequential Read/Write Operations
  • General Call Supported in Client Mode
  • Connection to DMA Controller Channels Optimizes Data Transfers
    • One channel for the receiver
    • One channel for the transmitter
    • Supports DMA data chunk transfer
  • Functional Safety: Protection, Monitors and Reports
    • Register Write protection
    • Reports any write-protected access
    • TWD and TWCK pad output integrity check
    • Triggers an interrupt on error
  • Note:
    1. See table TWI Compatibility with I2C Standard for further details.