Jump to main content
Up to 1-GHz Arm® Cortex®-A7, MIPI/LVDS Display, Dual Gigabit Ethernet, Audio and Security
Search
Product Pages
SAMA7D65
Home
6
Image Subsystem
6.2
LCD Controller (LCDC)
6.2.6
Functional Description
6.2.6.22
Output Format
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
6.1
Overview
6.2
LCD Controller (LCDC)
6.2.1
Description
6.2.2
Embedded Characteristics
6.2.3
Block Diagram
6.2.4
I/O Lines Description
6.2.5
Product Dependencies
6.2.6
Functional Description
6.2.6.1
Timing Engine Configuration
6.2.6.2
Interrupt Software Operations
6.2.6.3
DMA Software Operations
6.2.6.4
Layer Software Configuration
6.2.6.5
RGB Frame Buffer Memory Bitmap
6.2.6.6
YCbCr Frame Buffer Memory Mapping
6.2.6.7
Contrast Brightness, Hue, and Saturation
6.2.6.8
Chroma Upsampling Unit
6.2.6.9
Striding
6.2.6.10
Gamma Correction
6.2.6.11
Interlaced Frame Content
6.2.6.12
Color Space Conversion Unit
6.2.6.13
Unified Scaling Engine
6.2.6.14
Color Combine Unit
6.2.6.15
LCDC PWM Controller
6.2.6.16
Register Write Protection
6.2.6.17
Fault Detection and Injection
6.2.6.18
LCD Overall Performance
6.2.6.19
Input FIFO
6.2.6.20
Output FIFO
6.2.6.21
Output Timing Generation
6.2.6.22
Output Format
6.2.6.22.1
Active Mode Output Pin Assignment
6.2.7
Register Summary
6.3
Low Voltage Differential Signaling Controller (LVDSC)
6.4
Display Serial Interface (DSI)
6.5
GPU2D Controller (GPU2DC)
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
6.2.6.22 Output Format
