6.2.7.67 High-End Overlay Configuration Register 1

This register can only be written if HEWPCFGE is cleared in the LCDC Write Protection Mode Register.

Name: LCDC_HEOCFG1
Offset: 0x00000394
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
        ILD 
Access R/W 
Reset 0 
Bit 2322212019181716 
        YCC422ROT 
Access R/W 
Reset 0 
Bit 15141312111098 
 YCCMODE[3:0]  CLUTMODE[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
 RGBMODE[3:0] GAMYCCENCLUTEN 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 24 – ILD Interlaced Content

ValueDescription
0

Progressive scan is used.

1 Interlaced Frame content is used and deinterlacing process is activated.

Bit 16 – YCC422ROT YCbCr 4:2:2 Rotation

ValueDescription
0

Chroma upsampling kernel is configured to use 0 and 180 degrees algorithm.

1

Indicates that the chroma upsampling kernel is configured to use the 4:2:2 rotation algorithm. This bit is relevant only when a rotation angle of 90 degrees or 270 degrees is used.

Bits 15:12 – YCCMODE[3:0] YCbCr Mode Input Selection

ValueNameDescription
0 32BPP_AYCBCR

32 bpp AYCbCr 444

1 16BPP_YCBCR_MODE0

16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 4:2:2

2 16BPP_YCBCR_MODE1

16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 4:2:2

3 16BPP_YCBCR_MODE2

16 bpp Cb(n)Y(+1)Cr(n)Y(n) 4:2:2

4 16BPP_YCBCR_MODE3

16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 4:2:2

5 16BPP_YCBCR_SEMIPLANAR

16 bpp Semiplanar 4:2:2 YCbCr

6 16BPP_YCBCR_PLANAR

16 bpp Planar 4:2:2 YCbCr

7 12BPP_YCBCR_SEMIPLANAR

12 bpp Semiplanar 4:2:0 YCbCr

8 12BPP_YCBCR_PLANAR

12 bpp Planar 4:2:0 YCbCr

Bits 9:8 – CLUTMODE[1:0] CLUT Mode Input Selection

ValueNameDescription
0 CLUT_1BPP

CLUT mode set to 1 bit per pixel

1 CLUT_2BPP

CLUT mode set to 2 bits per pixel

2 CLUT_4BPP

CLUT mode set to 4 bits per pixel

3 CLUT_8BPP

CLUT mode set to 8 bits per pixel

Bits 7:4 – RGBMODE[3:0] RGB Mode Input Selection

ValueNameDescription
0 12BPP_RGB_444

12 bpp RGB 444

1 16BPP_ARGB_4444

16 bpp ARGB 4444

2 16BPP_RGBA_4444

16 bpp RGBA 4444

3 16BPP_RGB_565

16 bpp RGB 565

4 16BPP_ARGB_1555

16 bpp ARGB 1555

5 18BPP_RGB_666

18 bpp RGB 666

6 18BPP_RGB_666PACKED

18 bpp RGB 666 PACKED

7 19BPP_ARGB_1666

19 bpp ARGB 1666

8 19BPP_ARGB_PACKED

19 bpp ARGB 1666 PACKED

9 24BPP_RGB_888

24 bpp RGB 888

10 24BPP_RGB_888_PACKED

24 bpp RGB 888 PACKED

11 25BPP_ARGB_1888

25 bpp ARGB 1888

12 32BPP_ARGB_8888

32 bpp ARGB 8888

13 32BPP_RGBA_8888

32 bpp RGBA 8888

Bit 2 – GAM Gamma Correction

When GAM = 1, writing in LCDC_HEOCLUT[0..255] has no effect.
ValueDescription
0

Gamma correction is disabled.

1

Gamma correction is enabled.

Bit 1 – YCCEN YCbCr Color Space Enable

ValueDescription
0

Color space is RGB.

1

Color space is YCbCr.

Bit 0 – CLUTEN CLUT Mode Enable

When CLUTEN = 1, writing in LCDC_HEOCLUT[0..255] has no effect.
ValueDescription
0

RGB mode is selected.

1

CLUT mode is selected.