3.2 SPI - Serial Peripheral Interface

A clarification has been made to the Operation - Client Mode - Buffer Mode section.

26.3.2.2.2 Buffer Mode

The SPI peripheral can be configured in Buffered mode by writing a ‘1’ to the Buffer Mode Enable (BUFEN) bit in the Control B (SPIn.CTRLB) register to avoid data collisions.

This mode will enable two receive buffers and one transmit buffer. Both will have separate interrupt flags, transmit complete and receive complete. Figure 26-1 shows the extra buffers.

When Buffer mode is enabled, it can work in two different ways. The Buffer Mode Wait for Receive (BUFWR) bit in the Control B (SPIn.CTRLB) register controls how the Buffer mode works. The details of how they work, including timing diagrams, are described below.

Note: When operating as a client in Buffered mode and the SPI clock is close to maximum frequency, the client may not be able to set up data in time for the first sample edge during back-to-back transfers. Refer to the Electrical Characteristics - SPI section for details.