24.13.17 Periodic Timer Event Generation Control A
| Name: | PITEVGENCTRLA |
| Offset: | 0x16 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVGEN1SEL[3:0] | EVGEN0SEL[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 0:3, 4:7 – EVGENnSEL Event Generator n Select
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | No event generated |
| 0x1 | DIV4 | CLK_RTC divided by 4 |
| 0x2 | DIV8 | CLK_RTC divided by 8 |
| 0x3 | DIV16 | CLK_RTC divided by 16 |
| 0x4 | DIV32 | CLK_RTC divided by 32 |
| 0x5 | DIV64 | CLK_RTC divided by 64 |
| 0x6 | DIV128 | CLK_RTC divided by 128 |
| 0x7 | DIV256 | CLK_RTC divided by 256 |
| 0x8 | DIV512 | CLK_RTC divided by 512 |
| 0x9 | DIV1024 | CLK_RTC divided by 1024 |
| 0xA | DIV2048 | CLK_RTC divided by 2048 |
| 0xB | DIV4096 | CLK_RTC divided by 4096 |
| 0xC | DIV8192 | CLK_RTC divided by 8192 |
| 0xD | DIV16384 | CLK_RTC divided by 16384 |
| 0xE | DIV32768 | CLK_RTC divided by 32768 |
| other | - | Reserved |