27.5.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INPUTLVL | SDASETUP | SDAHOLD[1:0] | FMPEN | FMEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 6 – INPUTLVL Input Voltage Transition Level
| Value | Name | Description |
|---|---|---|
| 0 | I2C | I2C input voltage transition level |
| 1 | SMBUS | SMBus 3.0 input voltage transition level |
Bit 4 – SDASETUP SDA Setup Time
This bit controls the number of cycles the SCL is stretched to ensure sufficient setup time on the SDA out signal. This bit is used when operating in client mode.
| Value | Name | Description |
|---|---|---|
| 0 | 4CYC | SDA setup time is four clock cycles |
| 1 | 8CYC | SDA setup time is eight clock cycles |
Bits 3:2 – SDAHOLD[1:0] SDA Hold Time
This bit field selects the SDA hold time for the TWI. See the Electrical Characteristics section for details.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | Hold time OFF |
| 0x1 | 50NS | Short hold time |
| 0x2 | 300NS | Meets the SMBus 2.0 specifications under typical conditions |
| 0x3 | 500NS | Meets the SMBus 2.0 across all corners |
Bit 1 – FMPEN Fast-mode Plus Enable
Writing a ‘1’ to this bit selects the 1 MHz bus speed for the
TWI in default configuration or the TWI
host in Dual mode configuration.
| Value | Name | Description |
|---|---|---|
| 0 | OFF | Operating in Standard mode or Fast mode |
| 1 | ON | Operating in Fast mode Plus |
Bit 0 – FMEN Fast-mode Enable
Writing this bit to ‘1’ when operating in host mode adjusts the
SCL duty cycle to comply with I2C specification in Fast mode. This
bit has no effect in client mode or if Fast-mode Plus is enabled.
| Value | Name | Description |
|---|---|---|
| 0 | OFF | SCL duty cycle operating according to Sm specification |
| 1 | ON | SCL duty cycle operating according to Fm specification |