3.1 I/O Multiplexing

Table 3-1. PORT Function Multiplexing
VQFN/TQFP 48-pin	VQFN/TQFP 32-pin	SPDIP/SSOP 28-pin	VQFN 28-pin	Pin name⁽¹⁾	Special	ADC0	ACn	DAC0	USARTn	SPI0	TWI0⁽³⁾	TCAn	TCBn	CCL	EVSYS
44	30	22	26	PA0	XTALHF1 EXTCLK				0, TxD	0, MOSI⁽²⁾	0, SDA(HC)⁽²⁾	0, WO0		LUT0, IN0
45	31	23	27	PA1	XTALHF2				0, RxD	0, MISO⁽²⁾	0, SCL(HC)⁽²⁾	0, WO1		LUT0, IN1
46	32	24	28	PA2		AIN22			0, XCK 0, TxD⁽²⁾		0, SDA(HC)	0, WO2	0, WO	LUT0, IN2	EVOUTA
47	1	25	1	PA3		AIN23			0, XDIR 0, RxD⁽²⁾		0, SCL(HC)	0, WO3	1, WO	LUT0, OUT
48	2	26	2	PA4		AIN24			0, TxD⁽²⁾	0, MOSI		0, WO4 1, WO0⁽²⁾
1	3	27	3	PA5		AIN25			0, RxD⁽²⁾	0, MISO		0, WO5 1, WO1⁽²⁾
2	4	28	4	PA6		AIN26			0, XCK⁽²⁾	0, SCK		1, WO2⁽²⁾		LUT0, OUT⁽²⁾
3	5	1	5	PA7	CLKOUT	AIN27	0, OUT 1, OUT		0, XDIR⁽²⁾	0, SS					EVOUTA⁽²⁾
4				PB0								0, WO0⁽²⁾ 1, WO0
5				PB1								0, WO1⁽²⁾ 1, WO1
6				PB2								0, WO2⁽²⁾ 1, WO2			EVOUTB
7				PB3								0, WO3⁽²⁾ 1, WO3
8				PB4								0, WO4⁽²⁾ 1, WO4	2, WO⁽²⁾
9				PB5								0, WO5⁽²⁾ 1, WO5	3, WO
10	6	2	6	PC0		AIN28			1, TxD	0, SCK⁽²⁾ 0, MOSI⁽²⁾		0, WO0⁽²⁾	2, WO	LUT1, IN0
11	7	3	7	PC1		AIN29			1, RxD 0, TxD⁽²⁾	0,SS⁽²⁾ 0, MISO⁽²⁾ 0, MOSI⁽²⁾		0, WO1⁽²⁾	3, WO⁽²⁾	LUT1, IN1
12	8	4	8	PC2		AIN30	0, AINN3 1, AINN3		1, XCK 0, RxD⁽²⁾	0, SCK⁽²⁾ 0, MISO⁽²⁾	0, SDA(C) 0, SDA(HC)⁽²⁾	0, WO2⁽²⁾		LUT1, IN2	EVOUTC
13	9	5	9	PC3		AIN31	0, AINP4 1, AINP4		1, XDIR 0,XCK⁽²⁾	0, SS⁽²⁾ 0, SCK⁽²⁾	0, SCL(C) 0, SCL(HC)⁽²⁾	0, WO3⁽²⁾		LUT1, OUT
14				VDD
15				GND
16				PC4					1, TxD⁽²⁾			0, WO4⁽²⁾ 1, WO0⁽²⁾
17				PC5					1, RxD⁽²⁾			0, WO5⁽²⁾ 1, WO1⁽²⁾
18				PC6			0, OUT⁽²⁾ 1, OUT⁽²⁾		1, XCK⁽²⁾		0, SDA(C)⁽²⁾	1, WO2⁽²⁾		LUT1, OUT⁽²⁾
19				PC7					1, XDIR⁽²⁾		0, SCL(C)⁽²⁾				EVOUTC⁽²⁾
20	10	6	10	PD0		AIN0	0, AINN1 1, AINN1					0, WO0⁽²⁾		LUT2, IN0
21	11	7	11	PD1		AIN1						0, WO1⁽²⁾		LUT2, IN1
22	12	8	12	PD2		AIN2	0, AINP0 1, AINP0					0, WO2⁽²⁾		LUT2, IN2	EVOUTD
23	13	9	13	PD3		AIN3	0, AINN0 1, AINP1					0, WO3⁽²⁾		LUT2, OUT
24	14	10	14	PD4		AIN4	1, AINP2		0, TxD⁽²⁾	0, MOSI⁽²⁾		0, WO4⁽²⁾ 1, WO0⁽²⁾
25	15	11	15	PD5		AIN5	1, AINN0		0, RxD⁽²⁾	0, MISO⁽²⁾		0, WO5⁽²⁾ 1, WO1⁽²⁾
26	16	12	16	PD6		AIN6	0, AINP3 1, AINP3	OUT	0, XCK⁽²⁾ 1, TxD⁽²⁾	0, SCK⁽²⁾		1, WO2⁽²⁾		LUT2, OUT⁽²⁾
27	17	13	17	PD7	VREFA	AIN7	0, AINN2 1, AINN2		0, XDIR⁽²⁾ 1, RxD⁽²⁾	0, SS⁽²⁾					EVOUTD⁽²⁾
28	18	14	18	VDD
29	19	15	19	GND
30				PE0		AIN8	0, AINP1			0, MOSI⁽²⁾		0, WO0⁽²⁾
31				PE1		AIN9				0, MISO⁽²⁾		0, WO1⁽²⁾
32				PE2		AIN10	0, AINP2			0, SCK⁽²⁾		0, WO2⁽²⁾			EVOUTE
33				PE3		AIN11				0, SS⁽²⁾		0, WO3⁽²⁾
34	20	16	20	PF0	XTAL32K1	AIN16			2, TxD			0, WO0⁽²⁾		LUT3, IN0
35	21	17	21	PF1	XTAL32K2	AIN17			2, RxD			0, WO1⁽²⁾		LUT3, IN1
36	22			PF2		AIN18			2, XCK			0, WO2⁽²⁾		LUT3, IN2	EVOUTF
37	23			PF3		AIN19			2, XDIR			0, WO3⁽²⁾		LUT3, OUT
38	24			PF4		AIN20			2, TxD⁽²⁾			0, WO4⁽²⁾	0, WO⁽²⁾
39	25			PF5		AIN21			2, RxD⁽²⁾			0, WO5⁽²⁾	1, WO⁽²⁾
40	26	18	22	PF6	RESET/HV
41	27	19	23	PF7	UPDI					0, SS⁽²⁾					EVOUTF⁽²⁾
42	28	20	24	VDD
43	29	21	25	GND

Note:

Pin names are of Pxn type, with x being the PORT instance (A, B, C, ...) and n the pin number. Notation for signals is PORTx_PINn. All pins can be used as event inputs.
Alternative pin positions.
TWI pins are marked HC if they can be used as TWI Host or Client pins and C if they only can be used as TWI Client pins.