22.5.6 Control Register E Set - Normal Mode

Use this register instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit location.

Name: CTRLESET
Offset: 0x05
Reset: 0x00
Property: -

Bit 76543210 
     CMD[1:0]LUPDDIR 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 3:2 – CMD[1:0] Command

This bit field is used for software control of update, restart, and Reset of the timer/counter. The command bit field always reads as ‘0’.

ValueNameDescription
0x0 NONE No command
0x1 UPDATE Force update
0x2 RESTART Force restart
0x3 RESET Force hard Reset (ignored if the timer/counter is enabled)

Bit 1 – LUPD Lock Update

Locking the update ensures that all buffers are valid before performing an update.

ValueDescription
0 The buffered registers are updated as soon as an UPDATE condition has occurred
1 No update of the buffered registers is performed, even though an UPDATE condition has occurred. This setting will not prevent an update issued by the Command bit field.

Bit 0 – DIR Counter Direction

Usually, this bit is controlled in hardware by the Waveform Generation mode or by event actions but can also be changed from the software.

ValueDescription
0 The counter is counting up (incrementing)
1 The counter is counting down (decrementing)