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Preliminary Data Sheet
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AVR64EA28
AVR64EA32
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21
WDT - Watchdog Timer
21.3
Functional Description
Introduction
Family Overview
Features
1
Block Diagram
2
Pinout
3
I/O Multiplexing and Considerations
4
Hardware Guidelines
5
Power Domains
6
Conventions
7
AVR® CPU
8
Memories
9
GPR - General Purpose Registers
10
Peripherals and Architecture
11
NVMCTRL - Nonvolatile Memory Controller
12
CLKCTRL - Clock Controller
13
SLPCTRL - Sleep Controller
14
RSTCTRL - Reset Controller
15
CPUINT - CPU Interrupt Controller
16
EVSYS - Event System
17
PORTMUX - Port Multiplexer
18
PORT - I/O Pin Configuration
19
BOD - Brown-out Detector
20
VREF - Voltage Reference
21
WDT - Watchdog Timer
21.1
Features
21.2
Overview
21.3
Functional Description
21.3.1
Initialization
21.3.2
Clocks
21.3.3
Operation
21.3.4
Sleep Mode Operation
21.3.5
Debug Operation
21.3.6
Synchronization
21.3.7
Configuration Change Protection
21.4
Register Summary
21.5
Register Description
22
TCA - 16-bit Timer/Counter Type A
23
TCB - 16-Bit Timer/Counter Type B
24
RTC - Real-Time Counter
25
USART - Universal Synchronous and Asynchronous Receiver and Transmitter
26
SPI - Serial Peripheral Interface
27
TWI - Two-Wire Interface
28
CRCSCAN - Cyclic Redundancy Check Memory Scan
29
CCL - Configurable Custom Logic
30
AC - Analog Comparator
31
ADC - Analog-to-Digital Converter
32
DAC - Digital-to-Analog Converter
33
UPDI - Unified Program and Debug Interface
34
Instruction Set Summary
35
Electrical Characteristics
36
Characteristics Graphs
37
Ordering Information
38
Package Drawings
39
Data Sheet Revision History
Microchip Information
21.3 Functional Description
