2 Peripheral Overview
The following table shows the peripheral overview of the entire AVR SD family.
| Feature |
AVR32SD20 |
AVR32SD28 AVR64SD28 |
AVR32SD32 AVR64SD32 |
AVR64SD48 |
|---|---|---|---|---|
| Pins | 20 | 28 | 32 | 48 |
| Max. frequency (MHz) | 20 | 20 | 20 | 20 |
| Clock Controller (CLKCTRL) with Clock Failure Detection (CFD) and Clock Frequency Measurement (CFM) | 1 | 1 | 1 | 1 |
| Clock Failure Detection (CFD) | 2 | 2 | 2 | 2 |
| Clock Frequency Measurement (CFM) | 2 | 2 | 2 | 2 |
| 16-bit Timer/Counter type A (TCA) | 1 | 1 | 1 | 1 |
| 16-bit Timer/Counter type B (TCB) | 4 | 4 | 4 | 4 |
| 12-bit Timer/Counter type D (TCD) | 1 | 1 | 1 | 1 |
| Real-Time Counter (RTC) | 1 | 1 | 1 | 1 |
| USART | 2 | 3 | 3 | 3 |
| SPI | 2 | 2 | 2 | 2 |
| TWI/I2C(1) | 1(1) | 1(1) | 2(1) | 2(1) |
| 10-bit ADC (channels) | 2 (13) | 2 (19) | 2 (19) | 2 (24) |
| Analog Comparator (AC) | 3 | 3 | 3 | 3 |
| Digital-to-Analog Converter (DAC) | 1 | 1 | 1 | 1 |
| Zero Cross Detector (ZCD) | 2 | 2 | 2 | 2 |
| Configurable Custom Logic Look-up Table (CCL LUT) | 6 | 6 | 6 | 6 |
| Error Controller (ERRCTRL) | 1 | 1 | 1 | 1 |
| Synchronous Watchdog Timer (SWDT) | 1 | 1 | 1 | 1 |
| Watchdog Timer (WDT) | 1 | 1 | 1 | 1 |
| Event System (EVSYS) channels | 6 | 6 | 6 | 6 |
| General Purpose I/O | 15 | 21 | 25 | 40 |
| PORT | PA[7:0], PC[3:1], PD[7:4] | PA[7:0], PC[3:0], PD[7:1], PF[1:0] | PA[7:0], PC[3:0], PD[7:1], PF[5:0] | PA[7:0], PB[5:0], PC[7:0], PD[7:0], PE[3:0], PF[5:0] |
| PORT pins with MVIO capability | PC[3:1] | PC[3:0] | PC[3:0] | PC[7:0] |
| External interrupts | 15 | 21 | 25 | 40 |
| CRCSCAN | 1 | 1 | 1 | 1 |
| Unified Program and Debug Interface (UPDI) | 1 | 1 | 1 | 1 |
Note:
- The TWI/I2C can operate simultaneously as host and client on different pins.