4 Electrical Specifications
Refer to the device specific data sheet for absolute maximum ratings.
| AC/DC Characteristics | Standard Operating Conditions Production Tested at +25°C | |||||
|---|---|---|---|---|---|---|
| Sym. | Characteristics | Min. | Typ. | Max. | Units | Conditions/Comments |
| Programming Supply Voltages and Currents | ||||||
| VDD | Supply Voltage (VDDMIN, VDDMAX) | 1.80 | — | 5.50 | V | (Note 1) |
| VPEW | Read/Write and Page Erase Operations | VDDMIN | — | VDDMAX | V | |
| VBE | Bulk Erase Operations | VBORMAX | — | VDDMAX | V | (Note 2) |
| IDDI | Current on VDD, Idle | — | — | 1.0 | mA | |
| IDDP | Current on VDD, Programming | — | — | 10 | mA | |
| IPP | VPP | |||||
| Current on MCLR/VPP | — | — | 600 | µA | ||
| VIHH | High Voltage on MCLR/VPP for Program/Verify Mode Entry | 7.9 | — | 9.0 | V | |
| TVHHR | MCLR Rise Time (VIL to VIHH) for Program/Verify Mode Entry | — | — | 1.0 | µs | |
| VIH | I/O Pins | |||||
| (ICSPCLK, ICSPDAT, MCLR/VPP) Input High Level | 0.8 VDD | — | VDD | V | ||
| VIL | (ICSPCLK, ICSPDAT, MCLR/VPP) Input Low Level | VSS | — | 0.2 VDD | V | |
| VOH | ICSPDAT Output High Level | VDD – 0.7 | — | — | V | IOH = 3 mA, VDD = 3.0V |
| VOL | ICSPDAT Output Low Level | — | — | VSS + 0.6 | V | IOL = 6 mA, VDD = 3.0V |
| Programming Mode Entry and Exit | ||||||
| TENTS | Programing Mode Entry Setup Time: ICSPCLK, ICSPDAT Setup Time before VDD or MCLR↑ | 100 | — | — | ns | |
| TENTH | Programing Mode Entry Hold Time: ICSPCLK, ICSPDAT Hold Time before VDD or MCLR↑ | 1 | — | — | ms | |
| Serial Program/Verify | ||||||
| TCKL | Clock Low Pulse Width | 100 | — | — | ns | |
| TCKH | Clock High Pulse Width | 100 | — | — | ns | |
| TDS | Data in Setup Time before Clock↓ | 100 | — | — | ns | |
| TDH | Data in Hold Time after Clock↓ | 100 | — | — | ns | |
| TCO | Clock↑ to Data Out Valid (during a Read Data command) | 0 | — | 80 | ns | |
| TLZD | Clock↓ to Data Low-Impedance (during a Read Data from NVM command) | 0 | — | 80 | ns | |
| THZD | Clock↓ to Data High-Impedance (during a Read Data from NVM command) | 0 | — | 80 | ns | |
| TDLY | Data Input not Driven to Next Clock Input (delay required between command/data or command/command) | 1.0 | — | — | µs | |
| TERAB | Bulk Erase Cycle Time | — | — | 11 | ms | Program, Config and ID |
| TERAS | Page Erase Cycle Time | — | — | 11 | ms | |
| TPDFM | Internally Timed DFM (EEPROM) Programming Operation Time | — | — | 11 | ms | EEPROM and Configuration Bytes |
| TPINT | Internally Timed Programming Operation Time | — | — | 75 | µs | Program Memory and User IDs |
| TEXIT | Time Delay when Exiting Program/Verify Mode | 1 | — | — | µs | |
Note:
- Bulk erased devices default to
Brown-out Reset enabled with BORV =
11(low trip point). VDDMIN is the VBOR threshold (with BORV =1) when performing Low-Voltage Programming on a bulk erased device to ensure that the device is not held in Brown-out Reset. - The hardware requires VDD to be above the BOR threshold, at the ~2.85V nominal setting, to perform Bulk Erase operations. This threshold does not depend on the BORV Configuration bit settings. Refer to the microcontroller device data sheet specifications for Min./Typ./Max. limits of the VBOR level.