1 Silicon Issue Summary

Legend
-
Erratum is not applicable.
X
Erratum is applicable.
Peripheral Short Description Valid for Silicon Revision
Rev. B(1) Rev. C
Device 2.2.1 Writing the OSCLOCK Fuse in FUSE.OSCCFG to ‘1’ Prevents Automatic Loading of Calibration Values X X
2.2.2 Write Operation Lost if Consecutive Writes to Specific Address Spaces X X
ADC 2.3.1 One Extra Measurement Performed After Disabling ADC Free-Running Mode X X
2.3.2 ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty Cycle X X
2.3.3 Pending Event Stuck When Disabling the ADC X X
CCL 2.4.1 Connecting LUTs in Linked Mode Requires OUTEN Set to ‘1’ X X
2.4.2 D-latch is Not Functional X X
2.4.3 The CCL Must be Disabled to Change the Configuration of a Single LUT X X
NVMCTRL 2.5.1 Wrong Reset Value of NVMCTRL.CTRLA Register X X
PORTMUX 2.6.1 Selecting Alternative Output Pin for TCA0 Waveform Output 0-2 also Changes Waveform Output 3-5 X X
RTC 2.7.1 Any Write to the RTC.CTRLA Register Resets the RTC and PIT Prescaler Counter X X
2.7.2 Disabling the RTC Stops the PIT X X
TCA 2.8.1 Restart Will Reset Counter Direction in NORMAL and FRQ Mode X X
TCB 2.9.1 Minimum Event Duration Must Exceed the Selected Clock Period X X
2.9.2 The TCA Restart Command Does Not Force a Restart of TCB X X
2.9.3 CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode X X
USART 2.10.1 TXD Pin Override Not Released When Disabling the Transmitter X X
2.10.2 Frame Error on a Previous Message May Cause False Start Bit Detection X X
2.10.3 Full Range Duty Cycle Not Supported When Validating LIN Sync Field X X
2.10.4 Open-Drain Mode Does Not Work When TXD is Configured as Output X X
Note:
  1. This revision is the initial release of the silicon.