4.2 Good Practices

The following is a list of suggestions for designing with high speed signals:

Use controlled impedance PCB traces that match the specified single-ended (50Ω) and differential (90Ω/100Ω) impedance.
Keep the trace lengths of the differential signal pairs as short as possible.
The differential signal pair traces should be trace-length matched and the maximum trace-length mismatch should not exceed the specified values. Match each differential pair per segment.
Maintain parallelism and symmetry between differential signals with the trace spacing required to achieve the specified differential impedance.
Maintain maximum possible separation between the differential pairs, any high speed clocks/periodic signals (CMOS/TTL) and any connector leaving the PCB (such as I/O connectors, control and signal headers, or power connectors).
Route differential signals on the signal layer nearest the ground plane using a minimum of vias and corners. This will reduce signal reflections and impedance changes. Use GND stitching vias when changing layers.
Route CMOS/TTL and differential signals on different layers, which should be isolated by the power and ground planes.
Avoid tight bends. When it becomes necessary to turn 90°, use two 135° turns or an arc instead of a single 90° turn.
Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices or ICs that use and/or generate clocks.
Stubs on differential signals should be avoided due to the fact that stubs will cause signal reflections and affect signal quality.
Keep the length of high speed clock and periodic signal traces that run parallel to high speed signal lines at a minimum to avoid crosstalk. Based on EMI testing experience, the minimum suggested spacing to clock signals is 50 mils.
Use a minimum of 20 mils spacing between the differential signal pairs and other signal traces for optimal signal quality. This helps to prevent crosstalk.
Route all high speed traces over continuous planes (VCC or GND), avoiding cross splits or openings in those planes.
For microstrip or stripline transmission lines, keep the spacing between adjacent signal paths at least twice the line width.
Keep all traces at least five line widths away from the edge of the board.
Follow the return path of each signal and keep the width of the return path under each signal path at least as wide, and preferably at least three times as wide, as the signal trace.
To reduce EMI, avoid routing switching signals across copper splits or openings in ground planes. Routing around them is preferable even if it results in longer paths.
Minimize the loop inductance between the power and ground paths.
Allocate power and ground planes on adjacent layers with as thin a dielectric as possible to create plane capacitance.
Route the power and ground planes as close as possible to the surface where the decoupling capacitors are mounted.
Supply voltages must be composed of planes only, not traces (except for very low current voltage rails such as VDDBU). Short connections (≈ 8 mils) are commonly used to attach vias to planes. Any connections required from supply voltages to vias for device pins or decoupling capacitors should be as short and as wide as possible to minimize trace impedance (20 mils trace width).