Introduction

The PIC18F06/16Q40 devices you have received conform functionally to the current device data sheet (DS40002216F), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F06/16Q40 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.

Table . Silicon Device Identification
Part Number	Device ID	Revision ID
Part Number	Device ID	A4	A5	A6	B1
PIC18F06Q40	0x75C0	0xA004	0xA005	0xA006	0xA041
PIC18F16Q40	0x75A0	0xA004	0xA005	0xA006	0xA041

Important: Refer to the Device/Revision ID section in the current “PIC18-Q40 Family Programming Specification” (DS40002185) for more detailed information on Device Identification and Revision IDs for your specific device.

Table . Silicon Issue Summary
Module	Feature	Item No.	Issue Summary	Affected Revisions
Module	Feature	Item No.	Issue Summary	A4	A5	A6	B1
Analog-to-Digital Converter with Computation	ADCC	ADC Cannot Operate in Certain Low-Power Conditions	ADC cannot operate in certain low-power conditions	X
Analog-to-Digital Converter with Computation	ADCC	Double Sample Conversions	Double Sample Conversions	X	X	X
Oscillator	XT mode	Maximum Clock Frequency Limited to 2 MHz for XT Mode	Maximum clock frequency limited to 2 MHz for XT mode	X
	Fail-Safe Clock Monitor	Enabling the FOSC Fail-Safe Clock Monitor Alongside the Primary or Secondary Oscillator Clock Monitor Causes Issues with Sleep	Enabling the FOSC Fail-Safe Clock Monitor alongside the Primary or Secondary Oscillator Clock Monitor causes issues in Sleep	X
	EC mode	Maximum Clock Frequency for EC Mode Is 32 MHz for V_DD < 2.0V	Maximum clock frequency for EC mode is 32 MHz for V_DD < 2.0V	X
I²C	I²C	The I2CxADR0/1/2/3 Registers Have Incorrect Reset Value	I2CxADR0/1/2/3 registers have incorrect Reset value	X
		The I²C Start and/or Stop Flags May Be Set When I²C Is Enabled	I²C Start and/or Stop Flags May be set when I²C is Enabled	X	X
		MDR Bit Is Not Cleared after Bus Time-Out	MDR bit is not cleared after Bus Time-out	X	X	X	X
		Bus Time-Out Not Detected Properly When External Host Clock Stretches	Bus Time-out not detected properly when External Host Clock stretches	X	X	X	X
		Clock Stretch Disable Not Working Properly	Clock Stretch Disable not working properly	X	X	X	X
		Bus Time-Out Causes False Start/Stop	Bus Time-out causes false Start/Stop	X	X	X	X
		CSTR Bit Is Not Cleared after Bus Time-Out	CSTR bit is not cleared after bus time-out	X	X	X	X
	Multi-Host Mode	Operating in Multi-Host Mode Will Cause Bus Failures	Operating in Multi-Host Mode will cause bus failures	X	X	X	X
Universal Asynchronous Receiver Transmitter	UART	UART TXDE Signal May Go Low Before the STOP Bit Has Been Entirely Transmitted	UART TXDE signal may go low before the STOP bit has been entirely transmitted	X	X	X
Universal Asynchronous Receiver Transmitter	UART	Asynchronous 9-bit UART Address Mode Address Mismatch	Asynchronous 9-bit UART Address Mode Address Mismatch	X	X	X
Signal Measurement TImer	SMT	Reset Bit	Reset Bit	X	X	X
PIC18 CPU	FSR Shadow Registers	FSR Shadow Registers Are Not Writable	FSR Shadow Registers are not writable	X	X	X
ICSP™	Low-Voltage Programming (LVP)	Low-Voltage Programming Not Possible	Low Voltage Programming is not possible when VDD is below BORV while BOR is enabled	X	X	X
Instruction Set	`PUSHL` Instruction	1.8.1	The `PUSHL` instruction incorrectly executes	X	X	X	X
Note: Only those issues indicated in the last column apply to the current silicon revision.