2 Current Flow Analysis for TP-PFC at Zero Crossing

Figure 2-1 shows a simplified schematic of a standard totem pole PFC connected to an electronic load for the purpose of Common-mode current analysis.

Q3 is on during the AC negative half-cycle, resulting in the connection of N to V_OUT, and consequently, the PFC is directly connected to the grid. Due to the connection of the Y-capacitors shown in Figure 2-1, a Common-mode loop is formed from V_OUT to PGND through PE. Within this Common-mode loop, a capacitive divider between V_OUT and PGND is established by C_Y-PFC and C_Y-LOAD, as illustrated in Figure 2-2.

The effective capacitance of these two capacitors in series is given by:

$C_T=\frac{C_{Y-LOAD}\times C_{Y-PFC}}{C_{Y-LOAD}+C_{Y-PFC}}$

The total charge stored in this series capacitor circuit is given by:

$Q_T=C_T\times V_{BUS}$

During the negative half-cycle, the voltage across each capacitor, referred to PGND, can be calculated as follows:

$V_{AC-NEG}\left(C_{Y-PFC}\right)=V_{OUT}\times \frac{C_T}{C_{Y-PFC}}$

$V_{AC-NEG}\left(C_{Y-LOAD}\right)=V_{OUT}\times \frac{C_T}{C_{Y-LOAD}}$

During the AC positive half-cycle, Q4 is closed, resulting in the connection of N to PGND. In this scenario, C_Y-PFC and C_Y-LOAD are connected in parallel, with one side connected to PGND and the other to PE, as shown in Figure 2-3.

Assuming that resistances in the Common-mode circuit are negligible, the total charge will be preserved, and will therefore be redistributed between the two capacitors, making the voltages across the capacitors equal.

Since the capacitors are in parallel, the larger capacitor needs more charge to maintain the same voltage across it as the smaller capacitor.

During the positive AC half-cycle, the charge on C_Y-LOAD is given by:

$Q_{AC-POS}\left(C_{Y-LOAD}\right)=Q_T\times \frac{C_{Y-LOAD}}{C_{Y-LOAD}+C_{Y-PFC}}$

The charge on C_Y-PFC is given by:

$Q_{AC-POS}\left(C_{Y-PFC}\right)=Q_T\times \frac{C_{Y-PFC}}{C_{Y-LOAD}+C_{Y-PFC}}$

The primary concern is the redistribution of the charge (QT) between C_Y-PFC and C_Y-LOAD during the transition from negative to positive AC (and vice versa), which results in short but very large currents flowing in the Common-mode loop. This can lead to EMI issues and cause distortion in the AC input current (between L and N) as it exists in the zero-crossing region, as shown in Figure 2-4.