1 Theory of Operation

Figure 1-1 illustrates the simplified circuit of the Power Factor Correction (PFC) stage connected to an electronic load. C_Y-PFC is the Y-capacitance of the PFC board (between Neutral and PE), and C_Y-LOAD is the Y-capacitance of the electronic load (between PGND and PE). The voltage between Neutral and PGND alternates between V_OUT and 0V, depending on the polarity of the AC voltage.

During the positive AC half-wave, Q4 is on and Q3 is off, so N is connected to PGND. Conversely, during the negative AC half-wave, Q3 is on and Q4 is off, so N is connected to V_OUT.

To manage the charge redistribution of the Y-capacitors, the current source scheme is added to the circuit. At the AC zero crossing, when transitioning from positive to negative current, GPIO_Y_H switches on for a brief period while GPIO_Y_L remains off, thus activating the upper current source. Conversely, during the zero-crossing transition from negative to positive current, GPIO_Y_L switches on for a short period while GPIO_Y_H remains off, thereby activating the lower current source.