Introduction

Microchip's PolarFire SoC FPGAs include the industry's RISC-V based Microprocessor Subsystem (MSS) and FPGA fabric that inherits all the features of the PolarFire family. The PolarFire SoC MSS includes 5x 64-bit RISC-V processor cores, AXI Switch, DDR Controller, Fabric Interface Controllers (FIC), and a rich set of peripherals. It also offers an unparalleled combination of low power consumption, thermal efficiency, and defence-grade security for smart, connected systems. It is the first SoC FPGA with a deterministic L2 memory subsystem enabling real-time applications. Built on the award-winning, mid-range, low power PolarFire FPGA architecture, PolarFire SoC devices deliver up to 50% lower power than alternative FPGAs, span from 25k to 460k logic elements, and feature 12.7G transceivers.

PolarFire SoC devices include L1 cache, L2 cache, DDR controller, and eNVM (embedded non-volatile memory) to execute user applications on U54 (Application Processor) cores. The L1 iCache can be used as ITIM (Instruction Tightly Integrated Memory) for code execution. The L2 Cache can be used as LIM (Loosely Integrated Memory) or Scratchpad. The external DDR memory such as LPDDR4 can also be interfaced using the DDR controller. The eNVM can be used for storing instructions and code execution. For more information, see PolarFire SoC FPGA MSS Technical Reference Manual.

This white paper describes CPU performance results based on the industry-standard performance benchmarking suites such as Dhrystone (Bare Metal), CoreMark (Bare Metal and Linux), and CoreMark-PRO (Linux) which are executed on the Application Processor Cores (U54, which uses RISC-V Architecture RV64GC) using the PolarFire SoC Icicle kit. The performance benchmarking suites are compiled with the GCC compiler on the RISC-V platform to evaluate the performance of embedded processors.

The following figure shows the execution methodology for the performance benchmarking suites. These performance suites are executed by applying different levels of optimization flags. All the computations are model-driven runtime (MDR), which uses all the aforementioned flags, trade-offs during the runtime to get the best performance results.

This white paper provides the summary of results after executing the benchmark applications from LIM, ITIM, eNVM, Scratchpad, and LPDDR4. The following table lists the system configuration common to all the performance benchmark suites.