3 Overview of Code Protection Features in 8-bit PIC Microcontrollers

The Program Flash Memory (PFM), Data Flash memory (DFM) or EEPROM and Configuration Bytes sections of 8-bit PIC microcontrollers contain the user’s proprietary application firmware, data and device configurations, which often require protection against unauthorized access and device malfunctioning.

The code protection features incorporated into 8-bit PIC microcontrollers effectively block any attempts to read or write to the program and data flash memory regions of a microcontroller.

The various sections of the device’s program memory can be categorized based on the type of data they store, read/write privileges, and level of protection offered by the 8-bit PIC microcontrollers.

Table 3-1 highlights the classification of 8-bit PIC microcontroller memory sections based on the type of data they store and the available protection features.

Table 3-1. Protection Features in 8-bit PIC Microcontrollers
Memory Region	Memory Section	Available Protection	Impact of Bulk Erase Operation
Program Flash Memory	Program Memory	Read and write	Completely erases the memory
Data Flash Memory	Data EEPROM	Read and write
Configuration Bytes	Configuration Bytes	Write
Program Flash Memory	User ID	No Protection
Device Configurations	DIA	No Protection	No Effect
	DCI
	Dev ID
	Rev ID

Table 3-2 highlights the protection features available for the different sections of device memory in the 8-bit PIC microcontrollers.

Table 3-2. Code Protection Features Offered for Various Memory Sections in 8-bit PIC Microcontrollers
Memory Region	Memory Section	Type of Protection	Associated Configuration Bit	Prohibited Action	Remarks
Program Flash Memory	Boot Block	Write^{(1, 3)}	WRTB	Write operation through ICSP and self-write operation	Bulk Erase operation through ICSP interface disable the read/ write protection
	Boot Block	Code^{(2, 3)}	CP	Read and write operations through ICSP
	Application Block	Write^{(1, 3)}	WRTAPP	Write operation through ICSP and self-write operation
	Application Block	Code^{(2, 3)}	CP	Read and write operations through ICSP
	SAF Block	Write^{(1, 3)}	WRTSAF	Write operation through ICSP and self-write operation
	SAF Block	Code^{(2, 3)}	CP	Read and write operations through ICSP
Data Flash Memory	Data EEPROM	Write^{(1, 3)}	WRTD	Write operation through ICSP and self-write operation
Data Flash Memory	Data EEPROM	Code^{(2, 3)}	CPD	Read and write operations through ICSP
Configuration Bytes	Configuration Bytes	Write^{(1, 3)}	WRTC	Write operation through ICSP and self-write operation

Note:

Self-write operation is not allowed.
Self-write operation is allowed.
Internal access through CPU to read the memory is allowed.

The code protection feature allows the device to be protected from unauthorized access. Both program memory protection (CP) and data memory protection (CPD) settings are referred to as code protection.

The CP Configuration bit protects the entire program memory space from external read and write operations. When CP = 0, external read and write operations of program memory are inhibited, and a read will return all zeros. The CPU can continue to read the program memory, regardless of the protection bit settings.

The CPD Configuration bit protects the entire data EEPROM memory space from external read and write operations. When CPD = 0, external read and write operations of the data EEPROM memory are inhibited, and a read will return all zeros.

The CP and CPD settings are controlled independently. Self-writes and NVM read functions to the program memory are unaffected by any of the code protection settings.

The write protection configuration bits protect the respective memory sections from self-write operations. Any attempts to write to a protected location will set the WRERR bit.

The code protection (CP, CPD) and write protection (WRTAPP, WRTSAF, WRTD, WRTC, WRTB) settings can be disabled through a Bulk Erase operation, which will also erase all memory locations.